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73s1210f self - contained smart card reader with pinpad and power management simplifying sys tem integration ? data sheet may 2009 rev. 1.4 ? 2009 teridian semiconductor corporation 1 general description the 73s1210f is a versatile and economical cmos system- on - chip device intended for smart card reader applications. the circuit is built around an 80515 high - performance core; it features primarily an iso - 7816 / emv interface and a generic asynchronous serial interface. delivered with turnkey teridian embedded firmware, it forms a ready - to - use smart card reader solution that can be seamlessly incorporated into any microprocessor - based system where a serial line is available. the solution is scalable, thanks to a built - in i 2 in addition, the circuit features an on/off mode which operates directly with an on/off system switch: any activity on the on/off button is debounced internally and controls the power generation circuit accordingly, under the supervision of the firmware (off request / off acknowledgement at firmware level). the off mode can be alternatively initiated from the controller (firmware action ins tead of on/off switch). c interface that allows to drive external electrical smart card interfaces such as teridian 73s8010 ics. this makes the solution immediately able to support multi - card slots or multi -sam architectures. in addition, the 73s1210 features a 5x6 pinpad interface, 8 user i/os, multiple interrupt options and an analog voltage input (for dc voltage monitoring such as battery level detection) that make it suitable for low - cost pinpad reader devices. the 80515 cpu core instruction set is compatible with the industry standard 8051, while offering one clock - cycle per instruction processing power (most instructions). with a cpu clock running up to 24mhz, it results in up to 24mips available that meets the requirements of various encryption needs such as aes, des / 3 - des and even rsa (for pin encryption for instance). the circuit requires a single 6mhz to 12mhz crystal. the respective 73s1210f embedded memories are 32kb flash program memory, 2kb user xram memory, and 256b iram memory. dedicated fifos for the iso 7816 uart are independent from the user xram and iram. alternatively to the turnkey firmware offered by teridian, customers can develop their own embedded firmware directly within their application or using teridian 7 3s1210f evaluation board through a jtag - like interface. the chip incorporates an inductor - based dc - dc converter that generates all the necessary voltages to the various 73s1210f function blocks (smart card interface, digital core, etc.) from any of two distinct power supply sources: t he +5v bus (v bus , 4.4 to 6.5v), or a main battery (v bat , 4.0v to 6.5v). the chip automatically powers - up the dc - dc converter with v bus if it is present, or uses v bat as the supply input if v bus is not present. alternatively, the pin v pc can support a wider power supply input range (2.7v to 6.5v), when using a single system supply source. in off mode, the circuit typically draws less than 1 a, which makes it ideal for applications where battery life must be maximized. embedded flash memory is in - system programmable and lockable by means of on - silicon fuses. this makes the 73s1210f suitable for both development and production phases. terid ian semiconductor corporation offers with its 73s1210f a very comprehensive set of software libraries for emv. refer to the 73s12xxf software users guide for a complete description of the application programming interface (api libraries) and related software modules. a complete array of development and programming tools, libraries and demonstration boards enable rapid development and certification of readers that meet most demanding smart card standards. applications ? pinpad smart card readers: o with serial connectivity o ideal for low - cost pos terminals and digital identification (secure login, govt id , ...) ? sim readers in personal wireless devices ? payphones & vending machines ? general purpose smart card readers advantages ? reduced bom ? versatile power supply options o 2.7v to 6.5v ranges ? higher performance cpu core (up to 24mips) ? built - in emv/iso slot, expandable to multi - slots ? flexible power supply options o on - chip dc - dc converter o cmos switches between supply inputs ? sub - a power down mode with on/off switch ? powerful in - circuit emulation and programming ? a complete set of emv4.1 / iso7816 libraries ? turnkey pc/sc firmware and host drivers o multiple os supported downloaded from: http:///
73s1210f data sheet ds_1210f_001 2 rev. 1.4 features 80515 core: ? 1 clock cycle per instruction (most instr uctions) ? cpu clocked up to 24mhz ? 32kb flash memory (lockable) ? 2kb xram (user data memory) ? 256 byte iram ? hardware watchdog timer oscillators: ? single low - cost 6mhz to 12mhz crystal ? an internal pll provides all the necessary clocks to each block of the syst em interrupts: ? standard 80c515 4 - priority level structure ? 9 different sources of interrupt to the core power down modes: ? 2 standard 80c515 power down and idle modes ? sub - a off mode ? on/off main system power switch: ? input for an spst momentary switch to ground timers: ? (2) standard 80c52 timers t0 and t1 ? (1) 16 - bit timer built - in iso - 7816 card interface: ? linear regulator produces vcc for the card (1.8v, 3v or 5v) ? full compliance with emv 4.1 ? activation/deactivation sequencers ? auxiliary i/o lines (c4 and c8 signals) ? 7kv esd protection on all interface pins communication with smart cards: ? iso 7816 uart 9600 to 115kbps for t=0, t=1 ? (2) 2 - byte fifos for transmit an d receive ? configured to drive multiple external teridian 73s8010x interfaces (for multi - sam architectures) voltage detection: ? analog input (detection range: 1.0v to 2.5v) communication interfaces: ? full - duplex serial interface (1200 to 115kbps uart) ? i 2 ? man - machine interface and i/os: c master interface (400kbps) ? 6x5 keyboard (hardware scanning, debouncing and scrambling) ? (8) user i/os ? single programmable current output (led) ? operating voltage: ? single supply 2.7v to 6.5v operation (vpc) ? 5v supply (vbus 4.4 v to 5.5v) with or without battery back up operation (vbat 4.0v to 6.5v) ? automated detection of voltage presence - priority on vbus over vbat dc - dc converter: ? requires a single 10 h inductor ? 3.3v / 20ma supply available for external circuits operating temperature: ? - 40c to 85c package: ? 68 - pin qfn, 44 pin qfn turnkey firmware: ? compliant with pc/sc, iso7816 and emv4.1 specifications ? features a power down mode accessible from the h ost ? supports plug & play over serial interface ? windows ? ? windows ce / mobile driver available (*) xp driver available (*) ? linux and other os: upon request ? or for custom developments: o a complete set of iso - 7816, emv4.1 and low - level libraries are available for t=0 / t=1 o two - level application programming interface (ansi c - language libraries) (*) contact teridian semiconductor for conditions and availability. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 3 table of contents 1 hardware description ................................................... ................................................... ................... 8 1.1 pin description ................................................... ................................................... ....................... 8 1.2 hardware overview ................................................... ................................................... ............. 11 1.3 80515 mpu co re ................................................... ................................................... ................. 11 1.3.1 80515 overview ................................................... ................................................... ....... 11 1.3.2 memory organization ................................................... ................................................. 11 1.4 p rogram security ................................................... ................................................... ................. 16 1.5 special function registers (sfrs) ................................................... ........................................ 18 1.5.1 internal data special function registers (sfrs) ................................................... ....... 18 1.5.2 iram special function registers (generic 80515 sfrs) ............................................ 19 1.5.3 external data special function registers (sfrs) ................................................... ..... 20 1.6 instruction set ................................................... ................................................... ...................... 22 1.7 peripheral descriptions ................................................... ................................................... ........ 22 1.7.1 oscillator and clock gen eration ................................................... ................................. 22 1.7.2 power supply management ................................................... ....................................... 25 1.7.3 power on/off ................................................... ................................................... ........ 26 1.7.4 power control modes ................................................... ................................................. 27 1.7.5 interrupts ................................................... ................................................... .................. 33 1.7.6 uart ................................................... ................................................... ....................... 40 1.7.7 timers and counters ................................................... .................................................. 45 1.7.8 wd timer (software watchdog timer) ................................................... ...................... 47 1.7.9 user (usr) ports ................................................... ................................................... ..... 49 1.7.10 analog voltage comparator ................................................... ....................................... 51 1.7.11 led driver ................................................... ................................................... ............... 53 1.7.12 i 2 c master interface ................................................... ................................................... . 54 1.7.13 keypad interface ................................................... ................................................... ...... 61 1.7.14 emulator port ................................................... ................................................... ........... 68 1.7.15 smart card interface function ................................................... ................................... 69 1.7.16 vdd fault detect function ................................................... ....................................... 103 2 typical application schematic ................................................... ................................................... 104 3 electrical specification ................................................... ................................................... ............. 105 3.1 absolute maximum ratings ................................................... .................................................. 105 3.2 recommended operating condit ions ................................................... .................................. 105 3.3 digital io characteristics ................................................... ................................................... ... 106 3.4 oscillator interface requirements ................................................... ........................................ 107 3.5 dc characteristics: analog input ................................................... .......................................... 107 3.6 smart card interface requirements ................................................... ..................................... 108 3.7 dc characteristics ................................................... ................................................... ............. 110 3.8 current fault detection circuits ................................................... ............................................ 111 4 equivalent circuits ................................................... ................................................... ................... 112 5 package pin designation ................................................... ................................................... ......... 120 5.1 68 - pin qfn pinout ................................................... ................................................... ............. 120 5.2 44 - pin qfn pinout ................................................... ................................................... ............. 121 6 packaging information ................................................... ................................................... ............. 122 6.1 68 - pin qfn package outline ................................................... ............................................... 122 6.2 44 - pin qfn package outline ................................................... ............................................... 123 7 ordering information ................................................... ................................................... ................ 124 8 related documentation ................................................... ................................................... ............ 124 9 contact info rmation ................................................... ................................................... .................. 124 revision history ................................................... ................................................... ................................ 125 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73s1210f data sheet ds_1210f_001 4 rev. 1.4 figures figure 1: ic functional block diagram ................................................... ................................................... ... 7 figure 2: memory map ................................................... ................................................... .......................... 15 figure 3: clock generation and control circuits ................................................... ..................................... 22 figure 4 : oscillator circuit ................................................... ................................................... ..................... 24 figure 5: detailed power management logic block diagram ................................................... ................. 25 figure 6: power down control ................................................... ................................................... .............. 27 figure 7: detail of power down interrupt logic ................................................... ....................................... 28 figure 8: power down sequencing ................................................... ................................................... ...... 29 figure 9: external interrupt configuration ................................................... ................................................ 33 figure 10: i 2 c write mode operation ................................................... ................................................... .... 55 figure 11: i 2 c read operation ................................................... ................................................... ............. 56 figure 12: simplified keypad block diagram ................................................... .......................................... 61 figure 13: keypad interface flow chart ................................................... .................................................. 63 figure 14: smart card interface block diagram ................................................... ...................................... 69 figure 15: external smart card interface block diagram ................................................... ....................... 70 figure 16: asynchronous activation sequence timing ................................................... ........................... 73 figure 17: deactivation sequence ................................................... ................................................... ........ 73 figure 18: smart card clk and etu gen eration ................................................... ................................... 74 figure 19: guard, block, wait and atr time definitions ................................................... ....................... 75 figure 20: synchronous activation ................................................... ................................................... ....... 77 figure 21: example of sync mode operation: generating/reading atr signals ..................................... 77 figure 22: creation of synchronous clock start/stop mode start bit in sync mode ................................ . 78 figure 23: creation of synchronous clock start/stop mode stop bit in sync mode ................................ . 78 figure 24: operation of 9 - bit mode in sync mode ................................................... ................................... 79 figure 25: 73s1210f typical application schematic ................................................... ............................ 104 figure 26: 12 mhz oscillator circuit ................................................... ................................................... ... 112 figure 27: 32khz oscillator circuit ................................................... ................................................... ..... 112 figure 28: digital i/o circuit ................................................... ................................................... ................ 113 figure 29: digital output circuit ................................................... ................................................... .......... 113 figure 30: digital i/o with pull up circuit ................................................... ............................................... 114 figure 31: digital i/o with pull down circuit ................................................... .......................................... 114 figure 32: digital input circuit ................................................... ................................................... ............. 115 figure 33: off_req interface circuit ................................................... .................................................. 115 figure 34: keypad row circuit ................................................... ................................................... ........... 115 figure 35: keypad column circuit ................................................... ................................................... ...... 116 figure 36: led circuit ................................................... ................................................... ......................... 116 figure 37: test and security pin circuit ................................................... ................................................ 117 figure 38: analog input circuit ................................................... ................................................... ........... 117 figure 39: smart card output circuit ................................................... ................................................... . 117 figure 40: smart card i/o circuit ................................................... ................................................... ....... 118 figure 41: pres input circuit ................................................... ................................................... ............. 118 figure 42: presb input circuit ................................................... ................................................... .......... 118 figure 43: on_off input circuit ................................................... ................................................... ........ 119 figure 44: 73s1210f 68 qfn pinout ................................................... ................................................... . 120 figure 45: 73s1210f 44 qfn pinout ................................................... ................................................... . 121 figure 46: 73s1210f 68 qfn mechanical drawing ................................................... .............................. 122 figure 47: 73s1210f 44 qfn package drawing ................................................... .................................. 123 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 5 tables table 1: 73s1210 pinout description ................................................... ................................................... ..... 8 table 2: mpu data memory map ................................................... ................................................... ......... 11 table 3: flash special function registers ................................................... ............................................. . 13 tab le 4: internal data memory map ................................................... ................................................... ..... 14 table 5: program security registers ................................................... ................................................... .... 17 table 6: iram special function registers locations ................................................... ............................. 18 table 7: iram special function registers reset values ................................................... ....................... 19 table 8: xram special function registers reset values ................................................... ...................... 20 table 9: psw register ................................................... ................................................... .......................... 21 table 10: port registers ................................................... ................................................... ....................... 21 table 11: frequencies and mcount values for mclk = 96mhz ................................................... ............. 23 table 12: the mclkctl register ................................................... ................................................... .......... 23 table 13: the tcon register ................................................... ................................................... .............. 24 table 14: the int5ctl register ................................................... ................................................... ............ 30 table 15: the misctl0 register ................................................... ................................................... ............ 30 table 16: the misctl1 reg ister ................................................... ................................................... ............ 31 table 17: the mclkctl register ................................................... ................................................... .......... 31 table 18: the pcon register ................................................... ................................................... .............. 32 table 19: the ien0 register ................................................... ................................................... ................ 34 table 20: the ien1 register ................................................... ................................................... ................ 35 table 21: the ien2 register ................................................... ................................................... ................ 35 table 22: the tcon register ................................................... ................................................... .............. 36 table 23: the t2con register ................................................... ................................................... ............ 36 table 24: the ircon regist er ................................................... ................................................... ............. 37 table 25: external mpu interrupts ................................................... ................................................... ........ 37 table 26: control bits for external interrupts ................................................... ........................................... 38 table 27: priority level groups ................................................... ................................................... ............ 38 table 28: the ip0 register ................................................... ................................................... ................... 38 table 29: the ip1 register ................................................... ................................................... ................... 39 table 30: priority levels ................................................... ................................................... ........................ 39 table 31: interrupt polling sequence ................................................... ................................................... .... 39 table 32: interrupt vectors ................................................... ................................................... ................... 39 table 33: uart modes ................................................... ................................................... ........................ 40 table 34: baud rate generation ................................................... ................................................... .......... 40 table 35: the pcon register ................................................... ................................................... .............. 41 table 36: the brcon register ................................................... ................................................... ........... 41 table 37: the misctl0 register ................................................... ................................................... ............ 42 table 38: the s0con register ................................................... ................................................... ............ 43 table 39: the s1con register ................................................... ................................................... ............ 44 table 40: the tmod register ................................................... ................................................... .............. 45 table 41: timers/counters mode description ................................................... ......................................... 45 table 42: the tcon register ................................................... ................................................... .............. 46 table 43: the ien0 register ................................................... ................................................... ................ 47 table 44: the ien1 register ................................................... ................................................... ................ 48 table 45: the ip0 register ................................................... ................................................... ................... 48 table 46: the wdtrel register ................................................... ................................................... ......... 48 table 47: direction registers and internal resources for dio pin groups ............................................... 49 table 48: udir control bit ................................................... ................................................... ................... 49 table 49: selectable controls using the uxis bits ................................................... .................................. 49 table 50: the usrintctl1 register ................................................... ................................................... ...... 50 table 51: the usrintctl2 register ................................................... ................................................... ...... 50 table 52: the usrintctl3 register ................................................... ................................................... ...... 50 table 53: the usrintctl4 register ................................................... ................................................... ...... 50 table 54: the acomp register ................................................... ................................................... ........... 51 table 55: the int6ctl register ................................................... ................................................... ............ 52 table 56: the ledctl register ................................................... ................................................... ............. 53 downloaded from: http:///
73s1210f data sheet ds_1210f_001 6 rev. 1.4 table 57: the dar register ................................................... ................................................... ................. 57 table 58: the wdr register ................................................... ................................................... ................ 57 table 59: the swdr register ................................................... ................................................... ............. 58 table 60: the rdr register ................................................... ................................................... ................. 58 table 61: the srdr register ................................................... ................................................... .............. 59 table 62: the csr register ................................................... ................................................... ................. 59 table 63: the int6ctl register ................................................... ................................................... ............ 60 table 64: the kcol register ................................................... ................................................... ............... 64 table 65: the krow register ................................................... ................................................... ............. 64 table 66: the kscan register ................................................... ................................................... ............ 65 table 67: the kstat register ................................................... ................................................... ............. 65 table 68: the ksize register ................................................... ................................................... .............. 66 table 69: the korderl register ................................................... ................................................... ....... 67 table 70: the korderh register ................................................... ................................................... ...... 67 table 71: the int5ctl register ................................................... ................................................... ............ 68 table 72: the scsel register ................................................... ................................................... .............. 80 table 73: the scint register ................................................... ................................................... ............... 81 table 74: the scie register ................................................... ................................................... ................ 82 table 75: the vccctl register ................................................... ................................................... .............. 83 table 76: the vcctmr register ................................................... ................................................... ............ 84 table 77: the crdctl register ................................................... ................................................... ............ 85 table 78: the stxctl register ................................................... ................................................... ............. 86 table 79: the stxdata register ................................................... ................................................... .......... 87 table 80: the srxctl register ................................................... ................................................... ............. 87 table 81: the srxdata register ................................................... ................................................... ......... 88 table 82: the scctl register ................................................... ................................................... ............... 89 table 83: the scectl register ................................................... ................................................... ............. 90 table 84: the scdir register ................................................... ................................................... ............. 91 table 85: the sprtcol register ................................................... ................................................... ............. 92 table 86: the scclk register ................................................... ................................................... ............ 93 table 87: the sceclk register ................................................... ................................................... .......... 93 table 88: the sparctl register ................................................... ................................................... ............ 94 table 89: the sbytectl register ................................................... ................................................... .......... 95 table 90: the fdreg register ................................................... ................................................... ............. 96 table 91: the fdreg bit functions ................................................... ................................................... ...... 96 table 92: divider ratios provided by the etu counter ................................................... .......................... 96 table 93: divider values for the etu clock ................................................... ............................................ 97 table 94: the crcmsb register ................................................... ................................................... ......... 98 table 95: the bgt register ................................................... ................................................... ................. 99 table 96: the egt register ................................................... ................................................... ................. 99 table 97: the bwtb0 register ................................................... ................................................... .......... 100 table 98: the bwtb1 register ................................................... ................................................... .......... 100 table 99: the bwtb2 register ................................................... ................................................... .......... 100 table 100: the bwtb3 register ................................................... ................................................... ........ 100 table 101: the cwtb0 register ................................................... ................................................... ........ 100 table 102: the cwtb1 register ................................................... ................................................... ........ 100 table 103: the atrlsb register ................................................... ................................................... ....... 101 table 104: the atrmsb register ................................................... ................................................... ...... 101 tab le 105: the ststo register ................................................... ................................................... ........ 101 table 106: the rlength register ................................................... ................................................... ....... 101 table 107: smart card sfr table ................................................... ................................................... ..... 102 table 108: the vddfctl register ................................................... ................................................... ...... 103 table 109: order numbers and packaging marks ................................................... ................................ 124 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 7 smart card iso interface sclk sio external smart card interface power regulation and vcc control logic gnd vdd tbus1 tbus2 tbus3 tbus0 rxtx erst isbr tclk txd rxd ice interface sec smart card logic iso uart and clock generator flash / rom program memory 32 kb data xram 2 kb core serial int 2 int 3 gnd gnd peripheral interface and sfr logic flash interface test ocdsi isr watch - dog timer pmu ports timer _0_1 memory _ control control unit ram _ sfr _ control alu reset voltage reference and fuse trim circuitry vpd regulator ana_in pll and timebases vdd scratch iram 256 b 12mhz oscillator x 12 out x 12 in col 4 col 3 col 2 col 1 col 0 row 5 row 4 row 3 row 2 row 1 row 0 keypad interface i 2 c master int . sda scl usr(8:0) drivers usr 7 usr 6 usr 5 usr 4 usr 3 usr 1 usr 2 usr 0 vcc rst clk i/o aux 2 aux 1 pres vpc gnd vbus vp vbat vdd lin off _ req on _ off gnd led driver led0 pins available on both 68 and 44 - pin packages . pins only available on 68 - pin package . figure 1 : ic functional block diagram downloaded from: http:///
73s1210f data sheet ds_1210f_001 8 rev. 1.4 1 hardware description 1.1 pin description table 1 : 73s1210 pinout description pin name pin (68 qfn) pin (44 qfn) type equivalent circuit* description x12in 10 9 i figure 26 mpu clock crystal oscillator input pin. a 1m ? resistor is required between pins x12in and x12out. x12out 11 10 o figure 26 mpu clock crystal oscillator output pin. r ow(5:0) 0 1 2 3 4 5 21 22 24 33 36 37 i figure 34 keypad row input sense. col(4:0) 0 1 2 3 4 12 13 14 16 19 o figure 35 keypad column output scan pins. usr(7:0) 0 1 2 3 4 5 6 7 35 34 32 31 30 29 23 20 22 21 20 19 18 17 14 13 io figure 30 general - purpose user pins, individually configurable as inputs or outputs or as external input interrupt ports. scl 5 6 o figure 29 i 2 c (master mode) compatible clock signal. note: the pin is configured as an open drain output. when the i2c interface is being used, an external pull up resistor is required. a value of 3k is recommended. sda 6 7 io figure 28 i 2 c (master mode) compatible data i/o. note: this pin is bi - directional. when the pin is configured as output, it is an open drain output. when the i2c interface is being used, an external pull up resistor is required. a value of 3k is recommended. rxd 17 11 i figure 32 serial uart receive data pin. txd 18 12 o figure 29 serial uart transmit data pin. int3 48 30 i figure 32 general purpose interrupt input. int2 49 31 i figure 32 general purpose interrupt input. sio 47 29 io figure 28 io data signal for use with external smart card interface circuit such as 73s8010. sclk 45 28 o figure 29 clock signal for use with external smart card interface circuit. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 9 pin name pin (68 qfn) pin (44 qfn) type equivalent circuit* description pres 53 34 i figure 41 smart card presence. active high. note: the pin has a very weak pull down resistor. in noisy environments, an external pull down may be desired to insure against a false card event. clk 55 36 o figure 39 smart c ard clock signal. rst 57 38 o figure 39 smart card reset signal. io 61 42 io figure 40 smart c ard data io signal. aux1 60 41 io figure 40 auxiliary smart card io signal (c4). aux2 59 40 io figure 40 auxiliary smart card io signal (c8). vcc 58 39 pso smart card vcc supply voltage output. a 0.47 f capacitor is required and should be located at the smart card connector. the capacitor should be a ceramic type with low esr. gnd 56 37 gnd smart card ground. vpc 65 44 psi power supply source for main voltage converter circuit. a 10 f and a 0.1 f capacitor are required at the vpc input. the 10 f capacitor should be a ceramic type with low esr. vbus 62 psi alternate power source input from external power supply. vbat 64 psi alternate power source input, typically from two series cells, v > 4v. vp 54 35 pso intermediate output of main converter circuit. requires an external 4.7 f low esr filter capacitor to gnd. lin 66 1 psi connection to 10 h inductor for internal step up converter. note: inductor must be rated for 400 ma maximum peak current. on_off 63 43 i figure 43 power control pin. connected to normally open spst switch to ground. closing switch for duration greater than debounce period will turn 73s1210f on. if 73s1210f is on, closing switch will flag the 73s1210f to go to the off state. firmware will control when the power is shut down. off_req 52 33 o figure 33 digital output. if on_off switch is closed (to ground) for debounce duration and circuit is on, off_req will go high (request to turn off). this output should be connected to an interrupt pin to signal the cpu core that a request to shut down power has been initiated. the firmware can then perform all of its shut down housekeeping duties before shutting down v dd . tbus(3:0) 0 1 2 3 50 46 44 41 io trace bus signals for ice. downloaded from: http:///
73s1210f data sheet ds_1210f_001 10 rev. 1.4 pin name pin (68 qfn) pin (44 qfn) type equivalent circuit* description rxtx 43 27 io ice control. erst 38 23 io ice control. isbr 3 io ice control. tclk 39 24 i ice control. ana_in 15 ai figure 38 analog input pin. this signal goes to a programmable comparator and is used to sense the value of an external voltage. sec 2 i figure 37 input pin for use in programming security fuse. it should be connected to ground when not in use. test 51 32 di figure 37 test pin, should be connected to ground led0 4 5 io figu re 36 special output driver, programmable pull - down current to drive led. may also be used as an input. vdd 68 28 40 3 16 25 pso v dd supply output pin. a 0.1 f capacitor is recommended at each vdd pin. n/c 7 8 26 27 no connect. gnd 9 25 42 67 2 8 15 26 gnd general ground supply pins for all io and logic circuits. reset 1 4 i figure 32 reset input, positive assertion. resets logic and registers to default condition. note: to insure proper reset ope ration after v dd is turned on by application of v bus power or activation of the on/off switch, external reset circuitry must generate a proper reset signal to the 73s1210f. this can be accomplished via a simple rc network. * see the figures in the equivalent circuits section. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 11 1.2 hardware overview the 73s1210f single smart card controller integrates all primary functional blocks r equired to implement a smart card reader. included on chip are an 8051 - compatible microprocessor (mpu) which executes up to one instruction per clock cycle (80515), a fully integrated is0 7816 compliant smar t card interface, expansion smart card interface, serial interface, i2c interface, 6 x 5 keypad inter face, ram, flash memory, and a variety of i/o pins. the power management circuitry provides a 3.3v voltage output (vdd, pin #68) that must be connected to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not internally connected). should external circuitry require a 3.3v digital power supply, the vdd output is capable of supplying additional current. figure 1 shows a functional block diagram of the 73s1210f . 1.3 80515 mpu core 1.3.1 80515 overview the 73s1210f includes an 80515 mpu (8 - bit, 8051 - compatible) that performs most instructions in one clock cycle. the 80515 architecture eliminates redundant bus states and implements parall el execution of fetch and execution phases. normally a machine cycle is aligned with a memory f etch, there fore, most of the 1 - byte instructions are performed in a single cycle. this leads to an 8x performance (average) improvement (in terms of mips) over the intel 8051 device running at the same clock frequency . actual processor clocking speed can be adjusted to the total processing demand of the applicati on (cryptographic calculations, key management, memory management, and i/o management) using the xram special function register mpuckctl . typical smart card, serial, keyboard and i2c management functions are available for the mpu as part of the teridian standard library. a standard ansi c 80515 - application programming interface library is available to help reduce design cycle. refer to the 73s12 xx f softwa re users guide . 1.3.2 memory organization the 80515 mpu core incorporates the harvard architecture with separate code and data spaces. memory organization in the 80515 is similar to that of the industry standard 8051. there are three memory areas: program memory (flash), external data memory (xram), and internal data memory (iram). data bus address space is allocated to on - chip memory as shown table 2 table 2 : mpu data memory map address (hex) memory technology memory type typical usage memory size (bytes) 0000 -7fff flash memory non - volatile program and non - volatile data 32kb 0000 - 07ff static ram volatile mpu data xram 2kb fc00-ffff external sfr volatile peripheral control 1kb note: the iram is part of the core and is addressed differently. program memory: the 80515 can address up to 32kb of program memory space from 0x0000 to 0xffff. program memory is read when the mpu fetches instructions or perform s a movc operation. after reset, the mpu starts progra m execution from location 0x0000. the lower part of the program memory includes reset and interrupt vectors. the interrupt vectors are spaced at 8 - byte intervals, starting from 0x0003. reset is located at 0x0000. flash memory: the program memory consists of flash memory. the flash memory is intended to primarily contain mpu program code. flash erasure is initiated by writing a s pecific data pattern to downloaded from: http:///
73s1210f data sheet ds_1210f_001 12 rev. 1.4 specific sfr registers in the proper sequence. these special pattern/sequence requirements prevent i nadvertent erasure of the flash memory. the mass erase sequence is: 1. write 1 to the flsh_meen bit in the flshctl register (sfr address 0xb2[1] ). 2. write pattern 0xaa to erase (sfr address 0x94) . note: the mass erase cycle can only be initiated when the ice port is enabled. the page erase sequence is: 1. write the page address to pgaddr (sfr address 0xb7[7:1]) . 2. write pattern 0x55 to erase (sfr address 0x94) . the pgaddr register denotes the page address for page erase. the page size is 512 (200h) bytes and there are 128 pages within the flash memory. the pgaddr denotes the upper seven bits of the flash memory address such that bit 7:1 of the pgaddr corresponds to bit 15:9 of the flash memory address. bit 0 of the pgaddr is not used and is ignored. the mpu may write to the flash memory. this is one of the non - volatile storage options available to the user. the flshct l sfr bit flsh_pwe (flash program write enable) differentiates 80515 data store instructions (movx@dptr,a) between f lash and xram writes. before setting flsh_pwe , all interrupts need to be disabled by setting eal = 1. table 3 shows the location and description of the 73s1210 flash - specific sfrs. any fla sh modifications must set the cpuclk to operate at 3.6923 mhz ( mpuclkctl = 0x 0c) before any flash memory operations are executed to insure the proper timing when modifying the flash memory. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 13 table 3 : flash special function registers register sfr address r/w description erase 0x94 w this register is used to initiate either the flash mass erase cycle or the flash page erase cycle. specific patterns are expected for erase in order to initiate the appropriate erase cycle (default = 0x00). 0x55 C initiate flash page erase cycle. must be proceeded by a write to pgaddr @ sfr 0xb7. 0xaa C initiate flash mass erase cycle. must be proceeded by a write to flsh_meen @ sfr 0xb2 and the debug port must be enabled. any other pattern written to erase will have no effect. pgaddr 0xb7 r/w flash page erase address register containing the flash memory page address (page 0 through 127) that will be erased during the page erase cycle (default = 0x00). note: the page address is shifted left by one bit (see detailed description above). must be re - written for each new page erase cycle. flshctl 0xb2 r/w bit 0 ( flsh_pwe ): program write enable: 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space (flash) @ dptr. this bit is automatically reset after each byte written to flash . writes to this bit are inhibited when interrupts are enabled. w bit 1 ( flsh_meen ): mass erase enable: 0 C mass erase disabled (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle. r/w bit 6 ( secure): enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. internal data memory: the internal data memory provides 256 bytes (0x00 to 0xff) of data memory. the internal data memory address is always one byte wide and can be accessed by either direc t or indirect addressing. the special function registers occupy the upper 128 bytes . this sfr area is available only by direct addressing. indirect addressing accesses the upper 128 bytes of internal ram. the lower 128 bytes contain working registers and bit - addressable memory. the lower 32 bytes form four banks of eight registers (r0 - r7). two bits on the program memory status word ( psw ) select which bank is in use. the next 16 bytes form a block of bit - addressable memory space at bit addresses 0x00 - 0x7f. all of the bytes in the lower 128 bytes are accessible through direct or indi rect addressing. table 4 shows the internal data memory map. downloaded from: http:///
73s1210f data sheet ds_1210f_001 14 rev. 1.4 table 4 : internal data memory map address direct addressing indirect addressing 0xff special function registers (sfrs) ram 0x80 0x7f byte - addressable area 0x30 0 x2f byte or bit - addressable area 0x20 0x1f register banks r0r7 (x4) 0x00 external data memory: while the 80515 can address up to 64kb of external data memory in the space from 0x0000 to 0xffff, only the memory ranges shown in figure 2 contain physical memory. the 80515 writes into external data memory when the mpu executes a movx @ri,a or mo vx @dptr,a instruction. the mpu reads external data memory by executing a movx a,@ri or movx a,@dptr instruction. there are two types of instructions, differing in whether they provide an eight - bit or sixteen - bit indirect address to the external data ram. in the first type (movx a,@ri), the contents of r0 or r1, in the current register bank, provide the eight lower - ordered bits of address. this method allows the user access to the first 256 bytes of the 2kb of external data ram. in the second type of movx instruction (movx a,@dptr ), the data pointer generates a sixteen - bit address. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 15 address use 0xffff peripheral control re gisters (128b) 0xff80 0xff7f smart card control (384b) 0xfe00 address use 0xfbff C 0x7fff flash program memory 32k bytes 0x0800 address use 0x07ff xram indirect access direct access 0xff byte ram sfrs 0x80 0x7f byte ram 0x48 0x47 bit/byte ram 0x20 0x1f register bank 3 0x18 0x17 register bank 2 0x10 0x0f register bank 1 0x08 0x07 register bank 0 0x0000 0x0000 0x00 program memory external data memory internal data memory figure 2 : memory map dual data pointer: the dual data pointer accelerates the block moves of data. the standard dptr is a 16 - bit register that is used to address external memory. in the 80515 core, the standard dat a pointer is called dptr, the second data pointer is called dptr1. the data pointer select bit chooses the active pointer. the data pointer select bit is located at the lsb of the dps iram special function register (dps.0). dptr is selected when dps.0 = 0 and dptr1 is selected when dps .0 = 1. the user switches between pointers by toggling the lsb of the dps register. all dptr - related instruc tions use the currently selected dptr for any activity. the second data pointer may not be supported by certain compilers. downloaded from: http:///
73s1210f data sheet ds_1210f_001 16 rev. 1.4 1.4 program security two levels of program and data security are available. each level requires a specifi c fuse to be blown in order to enable or set the specific security mode. mode 0 security is enabled by setting the secure bit (bit 6 of sfr register flshctl 0xb2). mode 0 limits the ice interface to only allow bulk erase of the flash program memory. all other ice operations are blocked. this guarantees the sec urity of the users mpu program code. security (mode 0) is enabled by mpu code that sets the secur e bit. the mpu code must execute the setting of the secure bit immediately after a reset to pr operly enable mode 0. this should be the first instruction after the reset vector jump has been executed. if the startup.a51 assembly file is used in an application, then it must be modified to set the secu re bit after the reset vector jump. if not using startup.a51, then this should be the first instruct ion in main(). once security mode 0 is enabled, the only way to disable it is to perform a global erase of the flash followed by a full circuit reset. once the flash has been erased and the reset has been executed, security m ode 0 is disabled and the ice has full control of the core. the flash can be reprogrammed after t he bulk erase operation is completed. global erase of the flash will also clear the data xram m emory. the security enable bit (secure) is reset whenever the mpu is reset. har dware associated with the bit only allows it to be set. as a result, the code may set the secure bit to enable the security mode 0 feature but may not reset it. once the secure bit is set, the code is prot ected and no external read of program code in flash or data (in xram) is possible. in order to invoke the secur ity mode 0, the secset0 (bit 1 of the xram sfr register secreg 0xffd7) fuse must be blown beforehand or the security mode 0 will not be enabled. the secset0 and secset1 fuses once blown, cannot be overridden. specifically, when secure is set: ? the ice is limited to bulk flash erase only. ? page zero of flash memory, the preferred location for the users preboot code, may not be page - erased by either mpu or ice. page zero may only be erased with global flash erase. note that global flash erase erases xram whether the secure bit is set or not. ? writes to page zero, whether by mpu or ice, are inhibited. security mode 1 is in effect when the secset1 fuse has been programmed (blown open). in security mode 1, the ice is completely and permanently disabled. the flash program memory and the mpu are not available for alteration, observation, nor control. as soon as the fuse has been blown, the ice is disabled. the testing of the secset1 fuse will occur during the reset and before the start of pre - boot and boot cycles. this mode is not reversible, nor recoverable. in order to blow t he secset1 fuse, the sec pin must be held high for the fuse burning sequence to be executed properly. the firmwar e can check to see if this pin is held high by reading the secpin bit (bit 5 of xra m sfr register secreg 0xffd7). if this bit is set and the firmware desires, it can blow the secset1 fuse. the burning of the secset0 does not require the sec pin to be held high. in order to blow the fuse for secset1 and secset0, a particular set of regist er writes in a specific order need to be followed. there are two additional registers that need to have a specific value w ritten to them in order for the desired fuse to be blown. these registers are fusectl (0xffd2) and trimpctl (0xffd1). the sequence for blowing the fuse is as follows: 1. write 0x54h to fusectl . 2. write 0x81h for security mode 0. note: only program one security mode at a time. write 0x82h for security mode 1. note: sec pin must be high for security mode 1. 3. write 0xa6 to trimpctl . 4. delay about 500 s. 5. write 0x00 to trimpctl and fusectl . downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 17 table 5 : program security registers register sfr address r/w description fl shctl 0xb2 r/w bit 0 ( flsh_pwe ): program write enable: 0 C movx commands refer to xram space, normal operation (default). 1 C movx @dptr,a moves a to program space (flash) @ dptr. this bit is automatically reset after each byte written to flash. writes to this bit are inhibited when interrupts are enabled. w bit 1 ( flsh_meen ): mass erase enable: 0 C mass erase disabled (default). 1 C mass erase enabled. must be re - written for each new mass erase cycle. r/w bit 6 ( secure): enables security provisions that prevent external reading of flash memory and ce program ram. this bit is reset on chip reset and may only be set. attempts to write zero are ignored. trimpctl 0xffd1 w 0x54 value will set up for security fuse control. all other values are reserved and should not be used. fusectl 0xffd2 w 0xa6 value will cause the selected fuse to be blown. all other values will stop the burning process. secreg 0xffd7 w bit 7 (paramsec): 0 C normal operation. 1 C enable permanent programming of the security fuses . r bit 5 (secpin): indicates the state of the sec pin. the sec pin is held low by a pull - down resistor. the user can force this pin high during boot sequence time to indicate to firmware that sec mode 1 is desired. r/w bit 1 (secset1): see the program security section. r/w bit 0 (secset0): see the program security section. downloaded from: http:///
73s1210f data sheet ds_1210f_001 18 rev. 1.4 1.5 special function registers (sfrs) the 73s1210f utilizes numerous sfrs to communicate with the 73s1210fs many peripherals. this results in the need for more sfr locations outside the direct address iram space ( 0x80 to 0xff). while some peripherals are mapped to unused iram sfr locations, additional sfrs for the smar t card and other peripheral functions are mapped to the top of the xram data space (0xfc00 to 0xffff) . 1.5.1 intern al data special function registers (sfrs) a map of the special function registers is shown in table 6. table 6 : iram special function registers locations hex \ bin x000 x001 x010 x011 x100 x101 x110 x111 bin / hex f8 ff f0 b f7 e8 ef e0 a e7 d8 brcon df d0 psw kcol krow kscan kstat ksize korderl korderh d7 c8 t2con cf c0 irco n c7 b8 ien1 ip1 s0relh s1relh bf b0 flshctl pgaddr b7 a8 ien0 ip0 s0rell af a0 a7 98 s0con s0buf ien2 s1con s1buf s1rell 9f 90 usr70 udir70 dps erase 97 88 tcon tmod tl0 tl1 th0 th1 mclkctl 8f 80 sp dpl dph dpl1 dph1 wdtrel pcon 87 only a few addresses are used, the others are not implemented. sfrs specific to t he 73s1210f are shown in bold print (gray background). any read access to unimplemented addresses will return undefined data, while most write access will have no effect. however, a few loc ations are reserved and not user configurable in the 73s1210f. writes to the unused sfr locations can affect the op eration of the core and therefore must not be written to. this applies to all t he sfr areas in both the iram and xram spaces. in addition, all unused bit locations within valid sfr registers must be left in their default (power on default) states. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 19 1.5.2 ir am special function registers (generic 80515 sfrs) table 7 shows the location of the sfrs and the value they assume at reset or power - up. table 7 : iram special function registers reset values name location reset value description sp 0x81 0x07 stack pointer dpl 0x82 0x00 data pointer low 0 dph 0x83 0x00 data pointer high 0 dpl1 0x84 0x00 data pointer low 1 dph1 0x85 0x00 data pointer high 1 wdtrel 0x86 0x00 watchdog timer reload register pcon 0x87 0x00 power control tcon 0x88 0x00 timer/counter co ntrol tmod 0x89 0x00 timer mode control tl0 0x8a 0x00 timer 0, low byte tl1 0x8b 0x00 timer 1, high byte th0 0x8c 0x00 timer 0, low byte th1 0x8d 0x00 timer 1, high byte mclkctl 0x8f 0x0a master clock control usr70 0x90 0xff user port data (7:0) udir70 0x91 0xff user port direction (7:0) dps 0x92 0x00 data pointer select register erase 0x94 0x00 flash erase s0con 0x98 0x00 serial port 0, control register s0buf 0x99 0x00 serial port 0, data buffer ien2 0x9a 0x00 interrupt enable register 2 s1con 0x9b 0x00 serial port 1, control register s1buf 0x9c 0x00 serial port 1, data buffer s1rell 0x9d 0x00 serial port 1, reload register, low byte ien0 0xa8 0x00 interrupt enable register 0 ip0 0xa9 0x00 interrupt priority register 0 s0rell 0xaa 0xd 9 serial port 0, reload register, low byte flshctl 0xb2 0x00 flash control pgaddr 0xb7 0x00 flash page address ien1 0xb8 0x00 interrupt enable register 1 ip1 0xb9 0x00 interrupt priority register 1 s0relh 0xba 0x03 serial port 0, reload register, high byte s1relh 0xbb 0x03 serial port 1, reload register, high byte ircon 0xc0 0x00 interrupt request control register t2con 0xc8 0x00 timer 2 control psw 0xd0 0x00 program status word kcol 0xd1 0x1f keypad column downloaded from: http:///
73s1210f data sheet ds_1210f_001 20 rev. 1.4 name location reset value description krow 0xd2 0x3f keypad row kscan 0xd3 0x00 keypad scan time kstat 0xd4 0x00 keypad control/status ksize 0xd5 0x00 keypad size korder l 0xd6 0x00 keypad column ls scan order korderh 0xd7 0x00 keypad column ms scan order brcon 0xd8 0x00 baud rate control register (only brcon.7 bit used) a 0xe0 0x00 accumula tor b 0xf0 0x00 b register 1.5.3 external data special function registers (sfrs) a map of the xram special function registers is shown in table 8. the smart card registers are listed separately in table 107 . table 8 : xram special function registers reset values name location reset value description dar 0x ff80 0x00 device address register (i 2 c) wdr 0x ff81 0x00 write data register (i 2 c) swdr 0x ff82 0x00 secondary write data register (i 2 c) rdr 0x ff83 0x00 read data register (i 2 c) srdr 0x ff84 0x00 secondary read data register (i 2 c) csr 0x ff85 0x00 control and status register (i 2 c) usrintctl1 0x ff90 0x00 external interrupt control 1 usrintctl2 0x ff91 0x00 external interrupt control 2 usrintctl3 0x ff92 0x00 external interrupt control 3 usrintctl4 0x ff93 0x00 external interrupt control 4 int5ctl 0x ff94 0x00 external interrupt control 5 int6ctl 0x ff95 0x00 external interrupt control 6 mpuckctl 0x ffa1 0x0c mpu clock control acomp 0x ffd0 0x00 analog compare register trimpctl 0x ffd1 0x00 trim pulse contr ol fusectl 0x ffd2 0x00 fuse control vddfctl 0x ffd4 0x00 vddfault control secreg 0x ffd7 0x00 security register misctl0 0x fff1 0x00 m iscellaneous control register 0 misctl1 0x fff2 0x10 miscellaneous control register 1 ledctl 0x fff3 0xff led control register accumulator (acc, a): acc is the accumulator register. most instructions use the accumulator to hol d the operand. the mnemonics for accumulator - specific instructions refer to accumulator as a, not acc. b register: the b register is used during multiply and divide instructions. it can also be us ed as a scratch - pad register to hold temporary data. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 21 program status word (psw): table 9 : psw register msb lsb cv ac f0 rs1 rs ov C p bit symbol function psw.7 cv carry flag. psw.6 ac auxiliary carry flag for bcd operations. psw.5 f0 general purpose flag 0 available for user. psw.4 rs1 register bank select control bits. the contents of rs1 and rs0 select the working register bank: rs1/rs0 bank selected location 00 bank 0 (0x00 C 0x07) 01 bank 1 (0x08 C 0x0f) 10 bank 2 (0x10 C 0x17) 11 bank 3 (0 x18 C 0x1f) psw.3 rs0 psw.2 ov overflow flag. psw.1 f1 general purpose flag 1 available for user. psw.0 p parity flag, affected by hardware to indicate odd / even number of one bits in the accumulator, i.e. even parity. stack pointer: the stack pointer (sp) is a 1 - byte register initialized to 0x07 after reset. this register is incremented before push and call instructions, causing the stack to begin at location 0x 08. data pointer: the data pointer (dptr) is 2 bytes wide. the lower part is dpl, and the highest is dph. it can be loaded as a 2 - byte register (mov dptr,#data16) or as two registers (e.g. mov dpl,#data8). it is generally used to access external code or data space (e.g. movc a,@a+dptr or movx a,@dptr respectively). program counter: the program counter (pc) is 2 bytes wide initialized to 0x0000 after reset. this register is incremented during the fetching operation code or when operating on data from program memory. note: the program counter is not mapped to the sfr area. port regi sters: the i/o ports are controlled by special function register usr70 . the contents of the sfr can be observed on corresponding pins on the chip. writing a 1 to any of the ports (s ee table 10 ) causes the corresponding pin to be at high level (3.3v), and writing a 0 causes the corresponding pin t o be held at low level (gnd). the data direction register udir70 define individual pins as input or output pins (see the user (usr) ports section for details). table 10 : port registers register sfr address r/w description usr70 0x90 r/w register for user port bit 7:0 read and write operations (pins usr0 usr7). udir7 0 0x91 r/w data direction register for user port bits 0:7. setting a bit to 0 means that the corresponding pin is an output. downloaded from: http:///
73s1210f data sheet ds_1210f_001 22 rev. 1.4 all ports on the chip are bi - directional. each consists of a latch (sfr usr70), an output driver, and an input buffer, therefore the mpu can output or read data through any of these ports if they are not used for alternate purposes. 1.6 instruction set all instructions of the generic 8051 microcontroller are supported. a complete lis t of the instruction set and of the associated o p- codes is contained in the 73s12 xx f software users guide . 1.7 peripheral descriptions 1.7.1 oscillator and clock generation the 73s1210f has one oscillator circuit for the main cpu clock. the main oscillator circuit is designed to operate with various crystal or external clock frequencies. an internal divider working in conjunction with a pll and vco provides a 96mhz internal clock within the 73s1210f. 96 mhz is the recommend ed frequency for proper operation of specific peripheral blocks such as the specific timers, iso 7816 uart and interfaces, step - up converter, and keypad. the clock generation and control circuits are shown in figure 3. vco phase freq det cpu clock divider 6 bits mclk 96mhz 1.5-48mhz mpu clock - cpclk smart card logic block clock scclk sclk clock prescaler 6bits sc/sce clock prescaler 6bits sel etu clock divider 12 bits cpuckdiv see sc clock descriptions for more accurate diagram etuclk mcount(2:0) keyclk i2cclk 1khz 400khz divide by 120 divider /93760 high xtal osc x12in x12out m divider /(2*n + 4) hclk hoscen 12.00mhz 12.00mhz div 2 iclk scckenb selsc divide by 96 clk1m 1mhz 7.386mhz 7.386mhz 3.6923mhz i2c_2x 800khz div 2 sceclk div 2 div 2 figure 3 : clock generation and control ci rcuits downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 23 the master clock control register enables different sections of the clock circ uitry and specifies the value of the vco mcount divider. the mclk must be configured to operate at 96mhz to ensure proper operation of some of the peripheral blocks according to the following formula: mclk = (mcount * 2 + 4) * f xtal = 96mhz mcount is configured in the mclkctl register must be bound between a value of 1 to 10. t he possible crystal or external clock frequencies for getting mclk = 96mhz are shown in table 11 . table 11 : frequencies and mcount values for mclk = 96mhz f xtal (mhz) mcount (n) 12.00 2 9.60 3 8.00 4 6.86 5 6.00 6 master clock control register (mclkctl): 0x8f ? 0x0a the mpu clock that drives the cpu core defaults to 3.6923mhz after reset. t he mpu clock is scalable by configuring the mpu clock control register. table 12 : the mclkctl register msb lsb hsoen kben scen C C mct.2 mct.1 mct.0 bit symbol function mclkctl.7 hsoen high - speed oscillator disable. when set = 1, disables the high - speed crystal oscillator and vco/pll system. do not set this bit = 1. mclkctl.6 kben 1 = disable the keypad logic clock. mclkctl.5 scen 1 = disable the smart card logic clock. mcl kctl.4 C mclkctl.3 C mclkctl.2 mct.2 this value determines the ratio of the vco frequency (mclk) to the high - speed crystal oscillator frequency such that: mclk = (mcount*2 + 4)* f xtal . the default value is mcount = 2h such that mclk = (2*2 + 4)*12.00mhz = 96mhz. mclkctl.1 mct.1 mclkctl.0 mct.0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 24 rev. 1.4 mpu clock control register (mpuckctl): 0xffa1 ? 0x0c table 13 : the tcon register msb lsb C C mdiv.5 mdiv.4 mdiv.3 mdiv.2 mdiv.1 mdiv.0 bit symbol function mpuckctl.7 C mpuckctl.6 C mpuckctl.5 mdiv.5 this value determines the ratio of the mpu master clock frequency to the vco frequency (mclk) such that mpuclk = mclk/(2 * (mpuckdiv(5:0) + 1)). do not use values of 0 or 1 for mpuckdiv(n). default is 0ch to set cpclk = 3.6923 mhz. mpuckctl.4 mdiv.4 mpuckctl.3 mdiv.3 mpuckctl.2 mdiv.2 mpuckctl.1 mdiv.1 mpuckctl.0 mdiv.0 the oscillator circuits are designed to connect directly to standard parallel resonant crystal in a pierce oscillator configuration. each side of th e crystal should include a 22pf capacitor to ground for both oscillator circuits and a 1m ? resistor is required across the 12mhz crystal. 73s1210f x12in x12out 12mhz 22pf 22pf 1m ? note: the crystal should be placed as close as possible to the ic, and vias should be avoided. figure 4 : oscillator circuit downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 25 1.7.2 power supply management the detailed power supply management logic block diagram is shown in figure 5. v bus v bat v bust h + - q q set clr d debounce circuit on_off dc-dc converter / pass through* delay circuit (por) en vpc vp vp vcc regulator lin off_req int3 mpu int pwrdn* *pwrdn bit in misctl0 vdd vcc power control vcc voltage select vcc enable pass through mode enable pten q q set clr s r nc no *pass through -> vp = vpc smart card power to optional external circuits 20ma max. vdd regulator vdd to internal circuits figure 5 : detailed power management logic block diagram the 73s1210f contains a power supply and converter circuit that takes power from any one of three sources; v pc , v bus , or v bat . v pc is specified to range from 2.7 to 6.5 volts. it can typically be supplied by a single cell battery with a voltage range of 2.7 to approximately 3.1 volts or by a standard supply of 3.3 or 5 volts . v bus is typically supplied by an external power supply and ranges in value from 4.4 to 5.5 vol ts (6.5v maximum). downloaded from: http:///
73s1210f data sheet ds_1210f_001 26 rev. 1.4 v bat is expected to be supplied from a battery of three to four series connected cells wit h a voltage value of 4.0 to 6.5 volts. v bat and v bus are internally switched to v pc by two separate fet switches configured as a spdt switch (break - before - make). they will not be enabled at the same time. v bus is automatically selected in lieu of v bat when v bus is present (i.e. v bus always has the priority). if v pc is provided and either v bat or v bus is also used, the source of v pc must be diode isolated from the v pc pin to prevent current flow from v bat or v bus into the v pc source. the power that is supplied to the v pc pin (externally or internally, i.e. through v bat or v bus C see above) is up - converted to the intermediate voltage v p utilizing an inductive, step -u p converter. a series power inductor (nominal value = 10 h) must be connected from v pc to the pin lin, and a 10 f low esr filter capacitor must be connected to v pc . v p requires a 4.7 f filter capacitor and will have a nominal value of 5.5 volts during normal operation. v p is used internally by the smart card electrical interface circuit and is regul ated to the desired smart card supply v cc voltage (can be programmed for values of 5v, 3v, or 1.8v). v p is also used internally to generate a 3.3v nominal, regulated power supply v dd . v dd is output on pin 68 and must be directly tied to all other v dd pins on the 73s1210f (pins 28 and 40). v dd powers all the digital logic, input/output buffering, and analog functions. it can also be used for external circui try: up to 20ma current can be supplied to external devices simultaneously to the 73s1210fs digital c ore maximum consumption. 1.7.3 power on/off the 73s1210f features an on_off input pin for a momentary contact, main - system on/off switch. the purpose of this switch is to place the circuit in a very low - power mode C the off mode C where all circuits are no longer powered, therefore allowing the lowest possible current consumption. when in off mode, an action on the on/off switch will turn - on the power supply of the digital core (v dd ) and apply a power - on - reset condition. alternatively, entering the off mode from the on mode requires firmware action. when in on mode, an action on the on/off switch will send a request to the cont roller that will have to be acknowledged (firmware action required) in order to enter the off state. when placed into the off state, the 73s1210f will consume minimum current from v pc and v bat ; v p and v dd will be unavailable (v dd out = 0v and v p = 0v). when in on mode, the 73s1210f will operate normally, with all the features described in this document available. v p and v dd will be available (v dd out = 3.3v and v p = 5.5v nominal). whenever v bus power is supplied, the circuit will be automatically in the on state. t he functions of the on/off switch and circuitry are overridden and the 73s1210f is in the on stat e with v p and v dd available. without v bus applied, the circuit is by default in the off state, and will respond only to the on_off pin. the on_off pin should be connected to an spst switch to ground. if the circuit i s off and the switch is closed for a debounce period of 50 - 100ms, the circuit will go into the on state wherein all functions are operating in normal fashion. if the circuit is in the on state and the on /off pin is connected to ground for a period greater than the debounce period, off_req will be asserted high and held regardless of the state of on/off. the off_req signal should be connected to one of the interrupt pins to signal the cpu core that a request to shutdown has been initiated. the firmwar e will acknowledge this request by setting the scpwrdn bit in the smart card v cc control/status register ( vccctl ) high after it has completed all shutdown activities. when scpwrdn is set high, the circuit will deactivate the smart card interface if required and turn off all analog functions and the v dd supply for the logic and companion circuits. the default state upon application of power is the off state unless p ower is supplied to the v bus supply. note that at any time, the firmware may assert scpwrdn and the downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 27 73s1210f will go into the off state (when v bus is not present). if the on/off switch function is not desired and the application does not need to shut down power on vdd, the on_off input can be permanently grounded which will automatically turn on vdd when power is supplied on any of the vpc, vbat or vbus power supply inputs. if power is applied to both v bat and v bus , the circuit will automatically consume power from only the v bus source. the 73s1210f will be unconditionally on when v bus is applied. if the v bus source is removed, the 73s1210f will switchover to the vbat input supply and remain in the on stat e. the firmware should assert scpwrdn based on no activity or v bus removal to reduce battery power consumption. when operating from v bus , and not calling for v cc , the step - up converter becomes a simple switch connecting v bus to v p in order to save power. note: when the on_off switch function is not needed, i.e. when the 73s1210f must be in an always - on state when using another supply than vbus (v pc or v bat ), some external discrete components are needed. 1.7.4 power control modes the 73s1210f contains circuitry to disable portions of the device and place it into a low er power standby mode or power down the 73s1210f into its off mode. the standby mode will stop the cor e, clock subsystem and the peripherals connected to it. this is accomplished by either shutti ng off the power or disabling the clock going to the block. the miscellaneous control registers misctl0 , misctl1 and the master clock control register ( mclkctl ) provide control over the power modes. the pwrd n bit in misctl0 will setup the 73s1210f for standby or off modes. depending on the state of the on/o ff circuitry and power applied to the vbus input, the 73s1210f will go into either standby mode or power off mode. if system power is provided by, vbus or the on/off circ uitry is in the on state, the mpu core will placed into standby mode. if the vbus input is not sourcing power and the on/off circuitry is in the off state, setting the pwrdn bit will shut down the converter and v p will turn off. the power down mode should only be initiated by setting the pwrdn bit in the misctl0 register and not by manipulating individual control bits in various registers. figure 6 shows how the pwrdn bit controls the various functions that comprise power down state. vddfault analog functions (vco, pll, reference and bias circuits, etc.) analog compare high speed osc misctl0 - pwrdn vddfctl - vddfen acomp - cmpen mclckctl - hosen smart card power scvccctl - scprdn + + + + these are the registers and the names of the control bits. these are the block references. pwrdn signal note : the pwrdn signal is not the direct version of the pwrdn bit. there are delays from assertion of the pwrdn bit to the assertion of the pwrdn signal (32 mpu clocks). refer to the power down sequence diagram. flash read pulse one-shot circuit misctl1 - frpen + figure 6 : power down control downloaded from: http:///
73s1210f data sheet ds_1210f_001 28 rev. 1.4 when the pwrdn bit is set, the clock subsystem will provide a delay of 32 m puclk cycles to allow the program to set the stop bit in the pcon register. this delay will enable the program to properly halt the core before the analog circuits shut down (high speed oscillator, vco/pll, voltage refer ence and bias ci rcuitry, etc.). the pdmux bit in sfr int5ctl should be set prior to setting the pwrdn bit in order to configure the wake up interrupt logic. the power down mode is de - asserted by any of the interrupts connected to external interrupts 0, 4 and 5 (external usr[0:7], smart card and keypad). these interrupt sources are ored together and routed through some delay logic into int0 to provide this func tionality. the interrupt will turn on the power to all sections that were shut off and start the clock subsystem. after the clock subsystem clocks start running, the mpuclk begins to clock a 512 count delay counter. when the counter times out, the interrupt will then be active on int0 and the program can res ume. figure 7 shows the detailed logic for waking up the 73s1210f from a power down state using these specif ic interrupt sources. figure 8 shows the timing associated with the power down mode. usr[7:0] control usrxintsrc set to 4(ext int0 high) or 6(ext int0 low) 1 0 int5 int4 resetb tc clr 9 bit cntr resetb ce pdmux (ff94h:bit7) mpu int0 pwrdn_analog q clr d pwrdn (fff1h:bit7) usr0 usr6 usr1 usr2 usr3 usr4 usr5 usr7 tc ce clr 5 bit cntr notes: 1. the counters are clocked by the mpuclk 2. tc - terminal count (high at overflow) 3. ce - count enable resetb figure 7 : deta il of power down interrupt logic downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 29 pwrdn bit pwrdn sig ext. event int0 to mpu mpu stop analog enable pll clocks t1 t2 t3 t4 t5 t6 t0 t7 t0 : mpu sets pwrdn bit. t1 : 32 mpu clock cycles after t0, the pwrdn sig is asserted, turning all analog functions off. t2 : mpu executes stop instruction, must be done prior to t1. t3 : analog functions go to off condition. no vref, pll/vco, ibias, etc. text text : an external event (rtc, keypad, card event, usb) occurs. t4 : pwrdn bit and pwrdn signal are cleared by external event. t5 : high-speed oscillator/pll/vco operating. t6 : after 512 mpu clock cycles, int0 to mpu is asserted. t7 : int0 causes mpu to exit stop condition. figure 8 : power down sequencing downloaded from: http:///
73s1210f data sheet ds_1210f_001 30 rev. 1.4 external interrupt control register (int5ctl): 0xff94 ? 0x00 table 14 : the int5ctl register msb lsb pdmux C C C C C kpien kpint bit symbol function int5ctl.7 pdmux when set = 1, enables interrupts from keypad (normally going to int5), smart card interrupts (normally going to int4), or usr(7:0) pins (int0) to cause interrupt on int0. the assertion of the interrupt to int0 is delayed by 512 mpu clocks to allow the analog circuits, including the clock system, to stabilize. this bit must be set prior to asserting the pwrdn bit in order to properly configure the interrupts that will wake up the circuit. this bit is reset = 0 when this register is read. int5ctl.6 C int5ctl.5 C int5ctl.4 C int5ctl.3 C int5ctl.2 C int5ctl.1 kpien keypad interrupt enable. int5ctl.0 kpint keypad interrupt flag. miscellaneous control register 0 (misctl0): 0xfff1 ? 0x00 table 15 : the misctl0 register msb lsb pwrdn C C C C C slpbk ssel bit symbol function misctl0.7 pwrdn this bit sets the circuit into a low - power condition. all analog (high - speed oscillator and vco/pll) functions are disabled 32 mpu clock cycles after this bit is set = 1. this allows time for the next instruction to s et the stop bit in the pcon register to stop the cpu core. the mpu is not operative in this mode. when set, this bit overrides the individual control bits that otherwise control power consumption. misctl0.6 C misctl0.5 C misctl0.4 C misctl0.3 C misctl0.2 C misctl0.1 slpbk uart loop back testing mode. misctl0.0 ssel serial port pins select. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 31 miscellaneous control register 1 (misctl1): 0xfff2 ? 0x10 table 16 : the misctl1 register msb lsb C C frpen flsh66 C C C C bit symbol function misctl1.7 C misctl1.6 C misctl1.5 frpen flash read pulse enable (low). if frpen = 1 , the flash read signal is passed through with no change. when frpen = 0 a one - shot circuit that shortens the flash read signal is enabled to save power. the flash read pulse will shorten to 40 or 66ns (approximate based on the setting of the flsh66 bit) in duration, regardless of the mpu clock rate. for mpu clock frequencies greater than 10mhz, this bit should be set high. misctl1.4 flsh66 when high, creates a 66ns flash read pulse, otherwise creates a 40ns read pulse when frpen is set. mi sctl1.3 C misctl1.2 C misctl1.1 C misctl1.0 C master clock control register (mclkctl): 0x8f ? 0x0a table 17 : the mclkctl register msb lsb hsoen kben scen C C mct.2 mct.1 mct.0 bit symbol function mclkctl.7 hsoen* high -s peed oscillator enable. when set = 1, disables the high - speed crystal oscillator and vco/pll system. this bit is not changed when the pwrdn bit is set but the oscillator/vco/pll is disabled. mclkctl.6 kben 1 = disable the keypad logic clock. this bit is not changed in pwrdn mode but the function is disabled. mclkctl.5 scen 1 = disable the smart card logic clock. this bit is not changed in pwrdn mode but the function is disabled. interrupt logic for card insertion/removal remains operable even with smart card clock disabled. mclkctl.4 C mclkctl.3 C mclkctl.2 mct.2 this value determines the ratio of the vco frequency (mclk) to the high - speed crystal oscillator frequency such that: mclk = (mcount*2 + 4)*fxtal. the default value is mcount = 2h su ch that mclk = (2*2 + 4)*12.00mhz = 96mhz. mclkctl.1 mct.1 mclkctl.0 mct.0 *note: the hsoen bit should never be set under normal circumstances. power down control s hould only be initiated via use of the pwrdn bit in misct l0 . downloaded from: http:///
73s1210f data sheet ds_1210f_001 32 rev. 1.4 power control register 0 (pcon): 0x87 ? 0x00 the smod bit used for the baud rate generator is set up via this register. table 18 : the pcon register msb lsb smod C C C gf1 gf0 stop idle bit symbol function pcon.7 smod if sm0d = 1, the baud rate is doubled. pcon.6 C pcon.5 C pcon.4 C pcon.3 gf1 general purpose flag 1. pcon.2 gf0 general purpose flag 1. pcon.1 stop sets cpu to stop mode. pcon.0 idle sets cpu to idle mode. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 33 1.7.5 interrupts the 80515 core provides 10 interrupt sources with four priority levels. each source has its own request flag(s) located in a special function register ( tcon , ircon , and scon ). each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in sfrs ien0 , ien1 , and ien2 . some of the 10 sources are multiplexed in order to expand the number of interrupt sources . these are described in more detail in the respective sections. external interrupts are the interrupts external to the 80515 core, i.e. signals that or iginate in other parts of the 73s1210f, for example the usr i/o, smart card interface, analog comparators, etc . the external interrupt configuration is shown in figure 9. usr int ctl usr int ctl usr int ctl scint wait timeout card event rxdata tx_event tx_sent tx_error rx_error card_det vcc_ok crdctl vccctl + scie vcc_tmr analog comp keypad i 2 c usr int ctl t0 t1 int0 int1 usr pads usr0 usr7 usr6 usr5 usr4 usr3 usr2 usr1 int2 int3 int pads int2 int3 serial ch 0 serial ch 1 serchan 0 int serchan 1 int int4 int5 ctl int6 ctl int5 int6 + during stop, idle when pwrdn bit is set mpu core vdd_fault + delay clear pwrdn bit pdmuxctl 1 0 figure 9 : external interrupt configuration downloaded from: http:///
73s1210f data sheet ds_1210f_001 34 rev. 1.4 1.7.5.1 interrupt overview when an interrupt occurs, the mpu will vector to the predetermined address as shown i n table 32 . once the interrupt service has begun, it can only be interrupted by a higher priority interrupt . the interrupt service is termin ated by a return from the reti instruction. when a reti is performed, the proc essor will return to the instruction that would have been next when the interrupt occurred. when the interrupt condition occurs, the processor will also indicate this by sett ing a flag bit. this bit is set regardless of whether the interrupt is enabled or disabled. each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. if the sample indicates a pending i nterrupt when the interrupt is enabled, then the interrupt request flag is set. on the next inst ruction cycle, the interrupt will be acknowledged by hardware forcing an lcall to the appropriate vector address. interrupt response will require a varying amount of time depending on the state of the mpu when the interrupt occurs. if the mpu is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. in other cases, the response time depends on the current i nstruction. the fastest possible response to an interrupt is 7 machine cycles. this includes one m achine cycle for detecting the interrupt and six cycles to perform the lcall. 1.7.5.2 special function registers for interrupts interrupt enable 0 register (ien0): 0xa8 ? 0x00 table 19 : the ien0 register msb lsb eal wdt C es0 et1 ex1 et0 ex0 bit symbol function ien0.7 eal eal = 0 C disable all interrupts. ien0.6 wdt not used for interrupt control. ien0.5 C ien0.4 es0 es0 = 0 C disable serial channel 0 interrupt. ien0.3 et1 et1 = 0 C disable timer 1 overflow interrupt. ien0.2 ex1 ex1 = 0 C disable external interrupt 1. ien0.1 et0 et0 = 0 C disable timer 0 overflow interrupt. ien0.0 ex0 ex0 = 0 C disable external interrupt 0. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 35 interrupt enable 1 register (ien1): 0xb8 ? 0x00 table 20 : the ien1 register msb lsb C swdt ex6 ex5 ex4 ex3 ex2 C bit symbol function ien1.7 C ien1.6 swdt not used for interrupt control. ien1.5 ex6 ex6 = 0 C disable external interrupt 6. ien1.4 ex5 ex5 = 0 C disable external interrupt 5. ien1.3 ex4 ex4 = 0 C disable external interrupt 4. ien1.2 ex3 ex3 = 0 C disable external interrupt 3. ien1.1 ex2 ex2 = 0 C disable external interrupt 2. ien1.0 C interrupt enable 2 register (ien2): 0x9a ? 0x00 table 21 : the ien2 register msb lsb C C C C C C C es1 bit symbol function ien2.0 es1 es1 = 0 C disable serial channel interrupt. downloaded from: http:///
73s1210f data sheet ds_1210f_001 36 rev. 1.4 timer/counter control register (tcon): 0x88 ? 0x00 table 22 : the tcon register msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. tcon.6 tr1 not used for interrupt control. tcon.5 tf0 timer 0 overflow flag. tcon.4 tr0 not used for interrupt control. tcon.3 ie1 interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed. cleared when an interrupt is processed. tcon.2 it1 interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for input pin to cause an interrupt. tcon.1 ie0 inter rupt 0 edge flag is set by hardware when the falling edge on external interrupt int0 is observed. cleared when an interrupt is processed. tcon.0 it0 interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input pin to cause interru pt. timer/interrupt 2 control register (t2con): 0xc8 ? 0x00 table 23 : the t2con register msb lsb C i3fr i2fr C C C C C bit symbol function t2con.7 C t2con.6 i3fr external interrupt 3 failing/rising edge flag. i3fr = 0 external interrupt 3 negative transition active. i3fr = 1 external interrupt 3 positive transition active. t2con.5 i2fr external interrupt 3 failing/rising edge flag. i2fr = 0 external interrupt 3 negative transition active. i2fr = 1 external interrupt 3 positive transition active. t2con.4 C t2con.3 C t2con.2 C t2con.1 C t2con.0 C downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 37 interrupt request register (ircon): 0xc0 ? 0x00 table 24 : the ircon register msb lsb C C ex6 iex5 iex4 iex3 iex2 C bit symbol function ircon.7 C ircon.6 C ircon.5 iex6 external interrupt 6 flag. ircon.4 iex5 external interrupt 5 flag. ircon.3 iex4 external interrupt 4 flag. ircon.2 iex3 external interrupt 3 flag. ircon.1 iex2 external interrupt 2 flag. ircon.0 C 1.7.5.3 external interrupts th e external interrupts (external to the cpu core) are connected as shown in table 25 . interrupts with multiple sources are ored together and individual interrupt source control is provided i n xram sfrs to mask the individual interrupt sources and provide the corresponding interrupt flags. multifunction usr [7:0] pins control interrupts 0 and 1. dedicated external interrupt pins int2 and int 3 control interrupts 2 and 3. the polarity of interrupts 2 and 3 is programmable in the mpu. interrupts 4, 5 and 6 have multiple peripheral sources and are multiplexed to one of these three interrupts. the peripheral functi ons will be described in subsequent sections. generic 80515 mpu literature states that interrupts 4 through 6 are defined as rising edge sensitive. thus, the hardware signals attached to interrupts 4, 5 and 6 are converted to rising edge level by the hardware. sfr (special function register) enable bits must be set to permit any of these i nterrupts to oc cur. likewise, each interrupt has its own flag bit that is set by the interrupt hardwar e and is reset automatically by the mpu interrupt handler. table 25 : external mpu interrupts external interrupt connection polarity flag reset 0 usr i/o high priority see usrintctlx automatic 1 usr i/o low priority see usrintctlx automatic 2 external interrupt pin int2 edge selectable automatic 3 external interrupt pin int3 edge selectable automatic 4 smart card interrupts n/a automatic 5 keypad n/a automatic 6 i 2 n/a c, v dd _fault, analog comp automatic note: interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of the corresponding register. to prevent any interrupts from being ignored, the register cont aining multiple interrupt flags should be stored temporary to allow each interrupt flag to be tested separat ely to see which interrupt(s) is/are pending. downloaded from: http:///
73s1210f data sheet ds_1210f_001 38 rev. 1.4 table 26 : control bits for external interrupts enable bit description flag bit description ex0 enable external interrupt 0 ie0 external interrupt 0 flag ex1 enable external interrupt 1 ie1 external interrupt 1 flag ex2 enable external interrupt 2 iex2 e xternal interrupt 2 flag ex3 enable external interrupt 3 iex3 external interrupt 3 flag ex4 enable external interrupt 4 iex4 external interrupt 4 flag ex5 enable external interrupt 5 iex5 external interrupt 5 flag ex6 enable external interrupt 6 iex6 external interrupt 6 flag 1.7.5.4 power down interrupt logic the 73s1210f contains special interrupt logic to allow int0 to wake up the cpu from a power down (cpu stop) state. see the power control modes section for det ails. 1.7.5.5 interrupt priority level structure all interrupt sources are combined in groups, as shown in table 27 . table 27 : priority level groups group 0 external interrupt 0 serial channel 1 interrupt 1 timer 0 interrupt C external interrupt 2 2 external interrupt 1 C external interrupt 3 3 timer 1 interrupt C external interrupt 4 4 serial channel 0 interrupt C external interrupt 5 5 C C external interrupt 6 each group of interrupt sources can be programmed individually to one of four priority lev els by setting or clearing one bit in the special function register ip0 and one in ip1. if requests of the same priority level are received simultaneously, an internal polling sequence as per table 31 determines which request is serviced first. ien enable bits must be set to permit any of these interrupts to occur. likewi se, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by t he mpu interrupt handler. interrupt priority 0 register (ip0): 0xa9 ? 0x00 table 28 : the ip0 register msb lsb C wdts ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 note: wdts is not used for interrupt controls. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 39 interrupt pr iority 1 register (ip1): 0xb9 ? 0x00 table 29 : the ip1 register msb lsb C C ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 ip1.0 table 30 : priority levels ip1.x ip0.x priority level 0 0 level0 (lowest) 0 1 level1 1 0 le vel2 1 1 level3 (highest) table 31 : interrupt polling sequence external interrupt 0 polling sequence serial channel 1 interrupt timer 0 interrupt external interrupt 2 external interrupt 1 external interrupt 3 timer 1 interrupt serial channel 0 interrupt external interrupt 4 external interrupt 5 external interrupt 6 1.7.5.6 interrupt sources and vectors table 32 shows the interrupts with their associated flags and vector addresses. table 32 : interrupt vectors interrupt request flag description interrupt vector address n/a chip reset 0x0000 ie0 external interrupt 0 0x0003 tf0 timer 0 interrupt 0x000b ie1 external interrupt 1 0x0013 tf1 timer 1 interrupt 0x001b ri 0/ti0 serial channel 0 interrupt 0x0023 ri1/ti1 serial channel 1 interrupt 0x0083 iex2 external interrupt 2 0x004b iex3 external interrupt 3 0x0053 iex4 external interrupt 4 0x005b iex5 external interrupt 5 0x0063 iex6 external interrupt 6 0x006b downloaded from: http:///
73s1210f data sheet ds_1210f_001 40 rev. 1.4 1.7.6 u art the 80515 core of the 73s1210f includes two separate uarts that can be programmed to communicate with a host. the 73s1210f can only connect one uart at a time since there is only one set of tx and rx pins. the misctl0 re gister is used to select which uart is connected to the tx and rx pins. eac h uart has a different set of operating modes that the user can select according to their needs. the uart is a dedicated 2 - wire serial interface, which can communicate with an external host processor at up to 115,200 bits/s. the tx and rx pins operate at the v dd supply voltage levels and should never exceed 3.6v. the operation of each pin is as follows: rx : serial input data is applied at this pin. conforming to rs - 232 standard, the bytes are input lsb first. the voltage applied at rx must not exceed 3.6v. tx : this pin is used to output the serial data. the bytes are output lsb first. the 73s1210f has several uart - related read/write registers. all uart transfers are pro gra mmable for parity enable, parity select, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 115200 bps. table 33 shows the selectable uart operation modes and table 34 shows how the baud rates are calculated. table 33 : uart modes uart 0 uart 1 mode 0 n/a start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator). mode 1 s tart bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1). start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator). mode 2 start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of f ckmpu. n/a mode 3 start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1). n/a note: parity of serial data is available through the p flag of the accumulator. s even - bit serial modes with parity, such as those used by the flag protocol, can be simulated by setting and reading bi t 7 of 8 - bit output data. seven - bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8 - bit serial modes with parity can be simulated by setting and reading the 9 th bit, using the control bits s0con3 and s1con3 in the s0con and s1con sfrs. table 34 : baud rate generation using timer 1 using internal baud rate generator serial interface 0 2 smod 2 * f ckmpu / (384 * (256 - th1)) smod * f ckmpu /(64 * (2 10 - s0rel)) serial interface 1 n/a f ckmpu /(32 * (2 10 - s1rel)) note: s0rel (9:0) and s1rel (9:0) are 10 - bit values derived by combining bits from the respective timer reload registers sxrelh (bits 1:0) and sxrell (bits 7:0). th1 is the high byte of timer 1. the smod bit is located in the pcon sfr. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 41 power control register 0 (pcon): 0x87 ? 0x00 the smod bit used for the baud rate generator is set up via this register. table 35 : the pcon register msb lsb smod C C C gf1 gf0 stop idle bit symbol function pcon.7 smod if sm0d = 1, the baud rate is doubled. pcon.6 C pcon.5 C pcon.4 C pcon.3 gf1 general purpose flag 1. pcon.2 gf0 general purpose flag 1. pcon.1 stop sets cpu to stop mode. pcon.0 idle sets cpu to idle mode. baud rate control register 0 (brcon): 0xd8 ? 0x00 the bsel bit used to enable the baud rate generator is set up via this register. table 36 : the brcon register msb lsb bsel C C C C C C C bit symbol function brcon .7 bsel if bsel = 0, the baud rate is derived using timer 1. if bsel = 1 the baud rate generator circuit is used. brcon .6 C brcon .5 C . brcon .4 C brcon.3 C brcon .2 C brcon .1 C brcon .0 C downloaded from: http:///
73s1210f data sheet ds_1210f_001 42 rev. 1.4 miscellaneous c ontrol register 0 (misctl0): 0xfff1 ? 0x00 transmit and receive (tx and rx) pin selection and loop back test configuration are set up via this register. table 37 : the misctl0 register msb lsb pwrdn C C C C C slpbk ssel bit symbo l function misctl0.7 pwrdn this bit places the 73s1210f into a power down state. misctl0.6 C misctl0.5 C misctl0.4 C misctl0.3 C misctl0.2 C misctl0.1 slpbk 1 = uart loop back testing mode. the pins txd and rxd are to be connected together externally (with slpbk =1) and therefore: slpbk ssel mode 0 0 normal using serial_0 0 1 normal using serial_1 1 0 serial_0 tx feeds serial_1 rx 1 1 serial_1 tx feeds serial_0 rx misctl0.0 ssel selects either serial_1 if set =1 or serial_0 if set = 0 to be connected to rxd and txd pins. 1.7.6.1 serial interface 0 the serial interface 0 can operate in 4 modes: ? mode 0 pin rx serves as input and output. tx outputs the shift clock. 8 bits are t ransmitted with lsb first. the baud rate is fixed at 1/12 of the crystal frequency. reception is initialized in mode 0 by setting the flags in s0con as follows: ri0 = 0 and ren0 = 1. in other modes, a start bit when ren0 = 1 starts receiving serial data. ? mode 1 pin rx serves as input, and tx serves as serial output. no external shift cl ock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the transmission, 8 data bits are available by reading s0buf, and st op bit sets the flag rb80 in the special function register s0con . in mode 1 either internal baud rate generator or timer 1 can be use to specify baud rate. ? mode 2 this mode is similar to mode 1, with two differences. the baud rate is fixed at 1/32 or 1/64 of oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (lsb first), a programmable 9 th bit, and a stop bit (1). the 9 th bit can be used to control the parity of the serial interface: at transmission, bit tb80 in s0con is output as the 9 th bit, and at receive, the 9 th bit affects rb80 in special function register s0con . downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 43 ? mode 3 the only difference between mode 2 and mode 3 is that in mode 3 either internal baud rate generator or timer 1 can be use to specify baud rate. the s0buf register is used to read/write data to/from the serial 0 interface. serial interface 0 control register (s0con): 0x9b ? 0x00 transmit and receive data are transferred via this register. table 38 : the s0con register msb lsb sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 bit symbol function s0con.7 sm0 these two bits set the uart0 mode: mod e description sm0 sm1 0 n/a 0 0 1 8- bit uart 0 1 2 9- bit uart 1 0 3 9- bit uart 1 1 s0con.6 sm1 s0con.5 sm20 enables the inter - processor communication feature. s0con.4 ren0 if set, enables serial reception. cleared by software to disable receptio n. s0con .3 tb80 the 9 th transmitted data bit in modes 2 and 3. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication etc.). s0con.2 rb80 in modes 2 and 3 it is the 9 th data bit received. in mode 1, if sm20 is 0, rb80 is the stop bit. in mode 0 this bit is not used. must be cleared by software. s0con.1 ti0 transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software. s0con.0 ri0 receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. downloaded from: http:///
73s1210f data sheet ds_1210f_001 44 rev. 1.4 1.7.6.2 serial interface 1 the serial interface 1 can operate in 2 modes: ? mode a this mode is similar to mode 2 and 3 of serial interface 0, 11 bits are transmit ted or received: a start bit (0), 8 data bits (lsb first), a programmable 9 th bit, and a stop bit (1). the 9 th bit can be used to control the parity of the serial interface: at transmission, bit tb81 in s1con is outputted as the 9th bit, and at receive, the 9th bit affects rb81 in special function register s1con . the only difference between mode 3 and a is that in mode a only the internal baud rate generator can be use to specify baud r ate. ? mode b this mode is similar to mode 1 of serial interface 0. pin rx serves as i nput, and tx serves as serial output. no external shift clock is used, 10 bits are transmitted: a start bi t (always 0), 8 data bits (lsb first), and a stop bit (always 1). on receive, a start bit synchronizes the transmission, 8 data bits are available by reading s1buf, and stop bit sets the flag rb81 in the special function regi ster s1con . in mode 1, the internal baud rate generator is use to specify the baud rate. the s1buf register is used to read/write data to/from the serial 1 interface. serial interface control register (s1con): 0x9b ? 0x00 the function of the serial port depends on the setting of the serial port control regist er s1c on. table 39 : the s1con register msb lsb sm C sm21 ren1 tb81 rb81 ti1 ri1 bit symbol function s1con.7 sm sets the uart operation mode. sm mode description baud rate 0 a 9- bit uart variable 1 b 8- bit uart variable s1con.6 C s1con.5 sm21 enables the inter - processor communication feature. s1con.4 ren1 if set, enables serial reception. cleared by software to disable reception. s1con .3 tb81 the 9 th transmitted data bit in mode a. set or cleared by the mpu, depending on the function it performs (parity check, multiprocessor communication, etc.). s1con.2 rb81 in mode b, if sm21 is 0, rb81 is the stop bit. must be cleared by software. s1con.1 ti1 transmit interrupt flag, set by hardware after completion of a serial transfer. must be cleared by software. s1con.0 ri1 receive interrupt flag, set by hardware after completion of a serial reception. must be cleared by software. multiprocessor operation mode: the feature of receiving 9 bits in modes 2 and 3 of serial interface 0 or in mode a of serial interface 1 can be used for multiprocessor communication. in this case, the slave processors have bit sm20 in s0con or sm21 in s1con set to 1. when the master processor outputs slaves address, it sets the 9 th bit to 1, causing a serial port receive interrupt in all the slaves. the slave processors compare the received byte with their network address. if there is a m atch, the addressed slave will clear sm20 or sm21 and receive the rest of the message, while other slaves w ill leave the sm20 or sm21 bit unaffected and ignore this message. after addressing the slave, the host will output the rest of the message with the 9 th bit set to 0, so no serial port receive interrupt will be generated in unselected slav es. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 45 1.7.7 timers and counter s the 80515 has two 16 - bit timer/counter registers: timer 0 and timer 1. these registers can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, meaning that it c ounts up after every 12 periods of the mpu clock signal. in counter mode, the register is incremented when the falling edge is observed at the corres ponding input signal t0 or t1 (t0 and t1 are the timer gating inputs derived from usr[0:7] pins, see the user (usr) ports section). since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/2 of the oscillator frequency. there are no restrictions on the duty cy cle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. four operating modes can be selected for timer 0 and timer 1. two special function regi sters (tmod and tcon) are used to select the appropriate mode. the timer 0 load registers are designated as tl0 and th0 and the timer 1 load registers are designated as tl1 and th1. timer/counter mode control register (tmod): 0x89 ? 0x00 table 40 : the tmod register msb lsb gate c/t m1 m0 gate c/t m1 m0 timer 1 timer 0 bits tr1 and tr0 in the tcon register start their associated timers when set. bit symbol function tmod.7 tmod.3 gate if set, enables external gate control (usr pin(s) connected to t0 or t1 for counter 0 or 1, respectively). when t0 or t1 is high, and trx bit is set (s ee the tcon register ), a counter is incremented every falling edge on t0 or t1 input pin. if not set, the trx bit controls the corresponding timer. tmod.6 tmod.2 c/t selects timer or counter operation. when set to 1, the counter operation is performed based on the falling edge of t0 or t1. when cleared to 0, the corresponding register will function as a timer. tmod.5 tmod.1 m1 selects the mode for timer/counter 0 or timer/counter 1, as shown i n the tmod description. tmod.4 tmod.0 m0 selects the mode for timer/counter 0 or timer/counter 1, as shown in the tmod description. table 41 : timers/counters mode description m1 m0 mode function 0 0 mode 0 13 - bit counter/timer. 0 1 mode 1 16 - bit counter/timer. 1 0 mode 2 8- bit auto - reload counter/timer. 1 1 mode 3 if timer 1 m1 and m0 bits are set to '1', timer 1 stops. if timer 0 m1 and m0 bits are set to '1', timer 0 acts as two independent 8 - bit timer/counters. downloaded from: http:///
73s1210f data sheet ds_1210f_001 46 rev. 1.4 mode 0 putting either timer/counter into mode 0 configures it as an 8 - bit timer/counter with a divide - by - 32 prescaler. in this mode, the timer register is configured as a 13 - bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag tf0. the overflow flag tf0 then can be used to request an interrupt. the counted input is enabled to the timer when trx = 1 and either gate = 0 or tx = 1 (setting gate = 1 allows the timer to be controlled by external input tx, to facilit ate pulse width measurements). trx are control bits in the special function register tcon; gate is in tmod. the 13 - bit register consists of all 8 bits of th1 and the lower 5 bits of tl0. the upper 3 bits of tl0 are indeter minate and should be ignored. setting the run flag (trx) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. mode 1 mode 1 is the same as mode 0, except that the timer register is run with all 16 bi ts. mode 2 mode 2 configures the timer register as an 8 - bi t counter (tlx) with automatic reload. the overflow from tlx not only sets tfx, but also reloads tlx with the contents of thx, which is preset by software. the reload leaves thx unchanged. mode 3 mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply hol ds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as tw o separate counters. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0, and tf0. th 0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus , th0 now controls the "timer 1" interrupt. mode 3 is provided for applications requiring an extra 8 - bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any applic ation not requiring an interrupt from timer 1 itself. timer/counter control register (tcon): 0x88 ? 0 x00 table 42 : the tcon register msb lsb tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. tcon.6 tr1 not used for interrupt control. tcon.5 tf0 timer 0 overflow flag. tcon.4 tr0 not used for interrupt control. tcon.3 ie1 interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed. cleared when an interrupt is processed. tcon.2 it1 interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for input pin to cause an interrupt. tcon.1 ie0 interrupt 0 edge flag is set by hardware when the falling edge on external interrupt int0 is observed. cleared when an interrupt is processed. tcon.0 it0 interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input pin to cause interrupt. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 47 1.7.8 wd timer (software watchdog timer) the software watchdog timer is a 16 - bit counter that is incremented once every 24 or 384 clock cycles. after a reset, the watchdog timer is disabled and all registers are set to zero. the watchdog consists of a 16 - bit counter (wdt), a reload register ( wdtrel ), prescalers (by 2 and by 16), and control logic. once the watchdog starts, it cannot be stopped unless the internal reset signal becomes active. wd timer start procedure: the wdt is started by setting the swdt flag. when the wdt register enters the state 0x7cff, an asynchronous wdts signal will become active. the si gnal wdts sets bit 6 in the ip0 register and requests a reset state. wdts is cleared either by the r eset signal or by changing the state of the wdt timer. refreshing the wd timer: the watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. this requirement imposes an obligation on the programmer to issue two instructions. the first instruction sets wdt and the second instruction set s swdt. the maximum delay allowed between setting wdt and swdt is 12 clock cycles. if this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded wi th the content of the wdtrel register and wdt is automatically reset. interrupt enable 0 register (ien0): 0xa8 ? 0x00 table 43 : the ien0 register msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 bit symbol function ien0.7 eal eal = 0 C disable all interrupts. ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set directly before swd t is set to prevent an unintentional refresh of the watchdog timer. wdt is reset by hardware 12 clock cycles after it has been set. ien0.5 C ien0.4 es0 es0 = 0 C disable serial channel 0 interrupt. ien0.3 et1 et1 = 0 C disable timer 1 overflow interru pt. ien0.2 ex1 ex1 = 0 C disable external interrupt 1. ien0.1 et0 et0 = 0 C disable timer 0 overflow interrupt. ien0.0 ex0 ex0 = 0 C disable external interrupt 0. downloaded from: http:///
73s1210f data sheet ds_1210f_001 48 rev. 1.4 interrupt enable 1 register (ien1): 0xb8 ? 0x00 table 44 : the i en1 register msb lsb C swdt ex6 ex5 ex4 ex3 ex2 C bit symbol function ien1.7 C ien1.6 swdt watchdog timer start/refresh flag. set to activate/refresh the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. b it swdt is reset by the hardware 12 clock cycles after it has been set. ien1.5 ex6 ex6 = 0 C disable external interrupt 6. ien1.4 ex5 ex5 = 0 C disable external interrupt 5. ien1.3 ex4 ex4 = 0 C disable external interrupt 4. ien1.2 ex3 ex3 = 0 C disabl e external interrupt 3. ien1.1 ex2 ex2 = 0 C disable external interrupt 2. ien1.0 C interrupt priority 0 register (ip0): 0xa9 ? 0x00 table 45 : the ip0 register msb lsb C wdts ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 ip0.0 bit symbol function ip0.6 wdts watchdog timer status flag. set when the watchdog timer has expired. the internal reset will be generated, but this bit will not be cleared by the reset. this allows the user program to determine if the watchdog timer caused the reset to occur and respond accordingly. can be read and cleared by software. note: the remaining bits in the ip0 register are not used for watchdog control. watchdog timer reload register (wdtrel): 0x86 ? 0x00 table 46 : the wdtrel r egister msb lsb wdpsel wdrel6 wdrel5 wdrel4 wdrel3 wdrel2 wdrel1 wdrel0 bit symbol function wdtrel.7 wdpsel prescaler select bit. when set, the watchdog is clocked through an additional divide - by - 16 prescaler. wdtrel.6 to wdtrel.0 wdrel6 -0 seven bit reload value for the high - byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 49 1.7.9 user (usr) ports the 73s1210f includes 8 pins of general purpose digital i/o (gpio). on reset or power - up, all usr pins are inputs until they are configured for the desired direction. the pins are configured and c ontrolled by the usr70 and udir70 sfrs. each pin declared as usr can be configured independently as an input or output with the bits of the udir70 register. table 47 lists the direction registers and configurability associated with each group of usr pins. usr pins 0 to 7 are multiple use pins that can be used for general purpose i/o, external interrupts and timer control. table 48 shows the configuration for a usr pin through its associated bit in its udir register. values read from and written into the gpio ports use the data registers usr70 . note: after reset, all usr pins are defaulted as inputs and pulled up to vdd until any write to the corresponding udir register is performed. this insures all usr pins are set to a known value until set by the firmware. unused usr pins can be set for output if unused and unconnected to prevent them from floating. alternatively, unused usr pins can be set f or input and tied to ground or v dd . table 47 : direction registers and internal resources for dio pin groups usr pin group type direction register name direction re gister (sfr) location data register name data re gister (sfr) location usr_0usr_7 multi - use udir70 0x91 [7:0] usr70 0x90 [7:0] table 48 : udir control bit udir bit 0 1 usr pin function output input four xram sfr registers (usrinttctl0, usrinttctl1, usrint tctl2, and usrinttctl3) control the use of the usr [7:0] pins. each of the usr [7:0] pins can be configured as gpio or individually be assigned an internal resource such as an interrupt or a timer/counter control. each of the four registers contains two 3- bit configuration words named uxis (where x corresponds to the usr pin). the contr ol resources selectable for the usr pins are listed in table 50 through table 53 . if more than one input is connected to the same resource, the resources are combined using a logical or. table 49 : selectable controls using the uxis bits uxis value resource selected for usrx pin 0 none 1 none 2 t0 (counter0 gate/clock) 3 t1 (counter1 gate/clock) 4 interrupt 0 rising edge/high level on u srx 5 interrupt 1 rising edge/high level on usrx 6 interrupt 0 falling edge/low level on usrx 7 interrupt 1 falling edge/low level on usrx note: x denotes the corresponding usr pin. interrupt edge or level control is assigned i n the it0 and it1 bi ts in the tcon register. downloaded from: http:///
73s1210f data sheet ds_1210f_001 50 rev. 1.4 external interrupt control register (usrintctl1) : 0xff90 ? 0x00 table 50 : the usrintctl1 register msb lsb C u1is.6 u1is.5 u1is.4 C u0is.2 u0is.1 u0is.0 external interrupt control register (usrintctl2) : 0xff91 ? 0x00 table 51 : the usrintctl2 register msb lsb C u3is.6 u3is.5 u3is.4 C u2is.2 u2is.1 u2is.0 external interrupt control register (usrintctl3) : 0xff92 ? 0x00 table 52 : the usrintctl3 register ms b lsb C u5is.6 u5is.5 u5is.4 C u4is.2 u4is.1 u4is.0 external interrupt control register (usrintctl4) : 0xff93 ? 0x00 table 53 : the usrintctl4 register msb lsb C u7is.6 u7is.5 u7is.4 C u6is.2 u6is.1 u6is.0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 51 1.7.10 analog voltage compa rator the 73s1210f includes a programmable comparator that is connected to the ana_in pin. the comparator can be configured to trigger an interrupt if the input voltage rises above or fal ls below a selectable threshold voltage. the comparator control register should not be modified when the analog interrupt (anaien bit in the int6ctl register) is enabled to guard against any false interrupt that might be generated when modifying the threshold. the comparator has a built - in hysteresis to prevent the comparator from repeatedly responding to low - amplitude noise. this hysteresis is approximately 20mv. interrupt control is handled in the int6ctl register. analog compare control register (acomp): 0xff d0 ? 0x00 table 54 : the acomp register msb lsb analvl C onchg cpol cmpen tsel.2 tsel.1 tsel.0 bit symbol function acomp.7 analvl when read, indicates whether the input level is above or below the threshold. this is a real time value and is not latched, so it may change from the time of the interrupt trigger until read. acomp.6 C acomp.5 onchg if set, the ana_interrupt is invoked on any change above or below the threshold, bit 4 is ignored. acomp.4 cpol if set = 1, ana_interrupt is invoked when signal rises above selected threshold. if set = 0, ana_interrupt is invoked when signal goes below selected threshold (default). acomp.3 cmpen enables power to the analog comparator. 1 = enabled. 0 = disabled (default). acomp.2 ts el.2 sets the voltage threshold for comparison to the voltage on pin ana_in. thresholds are as follows: tsel.2 tsel.1 tsel.0 voltage threshold 0 0 0 1.00v 0 0 1 1. 24v 0 1 0 1. 40v 0 1 1 1.50v 1 0 0 1. 75v 1 0 1 2. 00v 1 1 0 2.30v 1 1 1 2. 50v acomp.1 tsel.1 acomp.0 tsel.0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 52 rev. 1.4 external interrupt control register ( int6ctl): 0xff95 ? 0x00 table 55 : the int6ctl register msb lsb C C vftien vftint i2cien i2cint anien anint bit symbol function int6ctl.7 C int6ctl.6 C int6ctl.5 vftien vdd fault interrupt enable. int6ctl.4 vftint vdd fault interrupt flag. int6ctl.3 i2cien i 2 c interrupt enabled. int6ctl.2 i2cint i 2 c interrupt flag. int6ctl.1 anien if anien = 1 analog compare event interrupt is enabled. when masked (anien = 0), anint (bit 0) may be set, but no interrupt is generated. int6ctl.0 anint (read only) set when the selected ana_in signal changes with respect to the selected threshold if compare_enable is asserted. cleared on read of register. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 53 1.7.11 led driver the 73s1210f provides a single dedicated output pin for driving a n led . th e led driver pin can be configured as a current source that will pull to ground to drive a n led that is connected to vdd without the need for an external current limiting resistor. this pin may be used as general pur pose output with the programmed pull - do wn current and a strong (cmos) pull - up, if enabled. the analog block must be enabled when this output is being used to drive the selected output current. this pin may be used as an input with consideration of the programmed output current and level. th e register bit when read, indicates the state of the pin. led control register (ledctl): 0xfff3 ? 0xff table 56 : the ledctl register msb lsb C lpuen iset.1 iset.0 C C C ledd0 bit symbol function ledctl.7 C ledctl.6 lpuen 0 = pull - ups are enabled for all of the led pins. ledctl.5 iset.1 these two bits control the drive current (to ground) for the led d river pin . current levels are: 00 = 0ma(off) 01 = 2ma 10 = 4ma 11 = 10ma ledctl.4 iset.0 ledctl.3 C ledctl.2 C ledctl.1 C ledctl.0 ledd0 write data controls output level of pin led0. read will report level of pin led0. downloaded from: http:///
73s1210f data sheet ds_1210f_001 54 rev. 1.4 1.7.12 i 2 c master interface the 73s1210f includes a dedicated fast mode, 400khz i 2 c master interface. the i 2 c interface can read or write 1 or 2 bytes of data per data transfer frame. the mpu communicates wi th the interface through six dedicated sfr registers: ? device address ( dar ) ? write data ( wdr ) ? secondary write data ( swdr ) ? read data ( rdr ) ? secondary read data ( srdr ) ? control and status ( csr ) the dar register is used to set up the slave address and specify if the transaction is a r ead or write operation. the csr register sets up, starts the transaction and reports any errors that may occur. when the i 2 c transaction is complete, the i 2 c interrupt is reported via external interrupt 6. the i 2 c interrupt is aut omatically de - asserted when a subsequent i 2 c transaction is started. the i 2 c interface uses a 400khz clock from the time - base circuits. 1.7.12.1 i 2 c write sequence to write data on the i 2 c master bus, the 80515 has to program the following registers according to the following sequence: 1. write slave device address to device address register ( dar ). the data contains 7 bits for the slave device address and 1 bit of op - code. the op - code bit should be written with a 0 to indicate a write operation. 2. write data to write data register ( wdr ). this data will be transferred to the slave device. 3. if writing 2 bytes, set bit 0 of the control and status register ( csr ) and load the second data byte to s econdary write data register ( swdr ). 4. set bit 1 of the csr register to start i 2 c master bus. 5. wait for i 2 c interrupt to be asserted. it indicates that the write on i 2 c master bus is done. refer to informat ion about the int6ctl , ien1 and ircon register for masking and flag operation. figure 10 shows the timing of the i 2 c write mode: downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 55 1-7 8 9 10-17 18 ack bit ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] write data [7:0 i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) 1-7 8 9 10-17 18 ack bit ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] write data [7:0] i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) secondary write data [7:0] ack bit 19-26 27 lsb msb figure 10 : i 2 c write mode operation 1.7.12.2 i 2 c read sequence to read data on the i 2 c master bus from a slave device, the 80515 has to program the following registers in this sequence: 1. write slave device address to device address register ( dar ). the data contains 7 bits device address and 1 bit of op - code. the op - code bit should be written with a 1. 2. write control data to control and status register. write a 1 to bit 1 to star t i 2 c master bus. also write a 1 to bit 0 if the secondary read data register ( srdr ) is to be captured from the i 2 c slave device. 3. wait for i 2 c interrupt to be asserted. it indicates that the read operation on the i 2 c bus is done. re fer to information about the int6ctl , ien1 and ircon registers for masking and flag operation. 4. read data from the read data register ( rdr ). 5. read data from secondary read data register ( srdr ) if bit 0 of control and status register ( csr ) is written with a 1. downloaded from: http:///
73s1210f data sheet ds_1210f_001 56 rev. 1.4 figure 11 shows the timing of the i 2 c read mode: 1-7 8 9 10-17 18 ack bit no ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] read data [7:0 i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) 1-7 8 9 10-17 18 ack bit no ack bit stop condition start condition scl sda lsb msb lsb msb device address [7:0] read data [7:0] i2c_interrupt start i2c (csr bit1) transfer length (csr bit0) secondary read data[7:0] ack bit 19-26 27 figure 11 : i 2 c read operation downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 57 device address register (dar): 0xff80 ? 0x00 table 57 : the dar register msb lsb dvadr.6 dvadr.5 dvadr.4 dvadr.3 dvadr.2 dvadr.1 dvadr.0 i2crw bit symbol funct ion dar.7 dvadr [0:6] slave device address. dar.6 dar.5 dar.4 dar.3 dar.2 dar.1 dar.0 i2crw if set = 0, the transaction is a write operation. if set=1, read. i2c write data register (wdr): 0xff81 ? 0x00 table 58 : the wdr register msb lsb wdr .7 wdr .6 wdr .5 wdr .4 wdr .3 wdr .2 wdr .1 wdr .0 bit function wdr .7 data to be written to the i 2 c slave device. wdr .6 wdr .5 wdr .4 wdr.3 wdr .2 wdr .1 wdr .0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 58 rev. 1.4 i2c secondary write data register (swdr): 0xff 82 ? 0x00 table 59 : the swdr register msb lsb swdr .7 swdr .6 swdr .5 swdr .4 swdr .3 swdr .2 swdr .1 swdr .0 bit function swdr .7 second data byte to be written to the i 2 c slave device if bit 0 (i2clen) of the control and status register ( csr ) is set = 1. swdr .6 swdr .5 swdr .4 swdr.3 swdr .2 swdr .1 swdr .0 i2c read data register (rdr): 0xff83 ? 0x00 table 60 : the rdr register msb lsb rdr .7 rdr .6 rdr .5 rdr .4 rdr .3 rdr .2 rdr .1 rdr .0 bit function rdr .7 data read from the i 2 c slave device. rdr .6 rdr .5 rdr .4 rdr.3 rdr .2 rdr .1 rdr .0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 59 i2c secondary read data register (srdr): 0xff84 ? 0x00 table 61 : the srdr register msb ls b srdr .7 srdr .6 srdr .5 srdr .4 srdr .3 srdr .2 srdr .1 srdr .0 bit function srdr .7 second data byte to be read from the i 2 c slave device if bit 0 (i2clen) of the control and status register ( csr ) is set = 1. srdr .6 srdr .5 srdr .4 srdr.3 srdr .2 srdr .1 srdr .0 i2c control and status register (csr): 0xff85 ? 0x00 table 62 : the csr register msb lsb C C C C C akerr i2cst i2clen bit symbol function csr.7 C csr.6 C csr.5 C csr.4 C csr.3 C csr.2 akerr set to 1 if acknowledge bit from slave device is not 0. automatically reset when the new bus transaction is started. csr.1 i2cst write a 1 to start i 2 c transaction. automatically reset to 0 when the bus transaction is done. this bit should be treated as a busy indicator on reading. if it is high, the serial read/write operations are not completed and no new address or data should be written. csr.0 i2clen set to 1 for 2 byte read or write operations. set to 0 for 1 - byte operations. downloaded from: http:///
73s1210f data sheet ds_1210f_001 60 rev. 1.4 ex ternal interrupt control register (int6ctl): 0xff95 ? 0x00 table 63 : the int6ctl register msb lsb C C vftien vftint i2cien i2cint anien anint bit symbol function int6ctl.7 C int6ctl.6 C int6ctl.5 vftien vdd fault interrupt e nable. int6ctl.4 vftint vdd fault interrupt flag. int6ctl.3 i2cien when set = 1, the i 2 c interrupt is enabled. int6ctl.2 i2cint when set = 1, the i 2 c transaction has completed. cleared upon the start of a subsequent i 2 c transaction. int6ctl.1 anien an alog compare interrupt enable. int6ctl.0 anint analog compare interrupt flag. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 61 1.7.13 keypad interface the 73s1210f supports a 30 - button (6 rows x 5 columns) keypad (spst mechanical contact switches) interface using 11 dedicated i/o pins. figure 12 shows a sim plified block diagram of the keypad interface. scan pull-up debouncing debounce time 7 6 5 4 3 2 1 0 ksize register 6 (1 ) kcol is normally used as read only register . when hardware keyscan mode is disabled , this register is to be used by firmware to write the column data to handle firmware scanning . key_detect hardware scan enable 6 column scan order 5 column value row value key_detect_enable korderl / h registers 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 kcol register (1) 7 6 5 4 3 2 1 0 krow register dividers 1 khz scan time kscan register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 kstat register keypad clock keypad clock vdd pull- up col 4:0 row5:0 73 s 1210 f if smaller keypad than 6 x 5 is to be implemented , unused row inputs should be connected to vdd . unused column outputs should be left unconnected . vdd figure 12 : simplified keypad block diagram there are five drive lines (outputs) corresponding to columns and 6 sense lines (inputs) corresponding to ro ws. hysteresis and pull - ups are provided on all inputs (rows), which eliminate the need for external resistors in the keypad. key scanning happens by asserting one of the 5 column lines low and looking for a low on a sense line indicating that a key is pressed (switch closed) at the inter section of the drive/sense (column/row) line in the keypad. key detection is performed by hardware with an incor porated debounce timer. debouncing time is adjustable through the kscan register . internal hardware circuitry performs column scanning at an adjustable scanning rate and column scanning order through registers kscan and korderl / korderh . key scanning is disabled at reset and must be enabled by firmware. when a valid key is detected, an interrupt is generated and the valid value of the pressed key i s automatically downloaded from: http:///
73s1210f data sheet ds_1210f_001 62 rev. 1.4 written into the kcol and krow reg isters. the keypad interface uses a 1khz clock derived from the 12mhz crystal . the clock is enabled by setting bit 6 C kben C in the mclkctl register ( see the oscillator and clock generati on section) to carry out scanning and debouncing. the keypad size can be adjusted within the ksize register. normal scanning is performed by hardware when the scnen bit is set at 1 in the kstat regis ter. figure 13 shows the flowchart of how the hardware scanning operates. in order to minimize power, scanning does not occur until a key - press is detected. once hardware key scanning is enabled, the hardware dri ves all column outputs low and waits for a low to be detected on one of the inputs. when a low is detected on any row, and before key scanning starts, the hardware checks that the low level is still detected after a debounce time. the debounce time is defined by firmware in the kscan register (bits 7:0, dbtime). debounce times from 4ms to 256ms in 4ms increments are supported. if a key is not pressed after the debounce time, the hardware will go back to looking for any input to be low . if a key is confirmed to be pressed, key scanning begins. key scanning asserts one of the 5 drive lines (col 4:0) low and looks for a low on a sense line indicating that a key is pressed at the intersection of the drive/sense line in the keypad. af ter all sense lines have been checked without a key - press being detected, the next column line is asserted. the time between checking each sense line is the scan time and is defined by firmware in the kscan register (bits 0 :1 C sctime). scan times from 1ms to 4ms are supported. scanning order does not aff ect the scan time. this scanning continues until the entire keypad is scanned. if only one key is pressed, a valid key is detected. simultaneous key presses are not considered as valid (if two keys are pres sed, no key is reported to firmware). possible scrambling of the column scan order is provided by means of the korderl and korderh registers that define the order of column scanning. values in these registers must be updated every time a new keyboard scan order is desired. it is not possible to change the order of scanning t he sense lines. the column and row intersection for the detected valid key are stored in the kcol and krow registers. when a valid key is detected, an interrupt is generated. firmware can then read those regi sters to determine which key had been pressed. after reading the kcol and krow registers, the firmware can update the korderl / korderh registers if a new scan order is needed. when the scnen bit is enabled in the kstat regis ter, the kcol and krow registers are only updated after a valid key has been identified. the hardware does not wait for the firmware to service the interrupt in order to proceed with the key scanning process. once the valid key (or invalid key C e.g. two keys pressed) is detected, the hardware waits for the key to be released. once the key is released, the debounce tim er is started. if the key is not still released after the debounce time, the debounce counter starts again. after a key release, all columns will be driven low as before and the process will repeat waiti ng for any key to be pressed. when the scnen bit is disabled, all drive outputs are set to the value i n the kco l register. if firmware clears the scnen bit in the middle of a key scan, the kcol register contains the last value stored in there which will then be reflected on the output pins. a bypass mode is prov ided so that the firmware can do the key scanning manually (scnen bit must be cleared). in bypass mode, the f irmware writes/reads the column and row registers to perform the key scanning. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 63 figure 13 : keypad interface flow chart any row input = 0 ? keypad initialization all column outputs = 0 deboucing timer any row input still = 0 ? yes no no how many keys have been detected ? download of the key row and column values in krow and kcol registers 1 key keypad interrupt generation is ( are ) the key (s ) released ? (*) deboucing timer yes is ( are) the key (s ) still released ? (*) no no kscan register : debouncing time kstat register : enable hw scanning enable keypad interrupt keypad scanning korderl / h registers : column scan order kstat register : key detect interrupt yes kcol register : value of the valid key column krow register : value of the valid key row kscan register : scanning rate ksize register : keypad size definition 0 key register used to control the hardware keypad interface register written by the hardware keypad interface more than 1 key kscan register : debouncing time (*) key release is cheked by looking for a low level on any row . downloaded from: http:///
73s1210f data sheet ds_1210f_001 64 rev. 1.4 keypad column reg ister (kcol): 0xd1 ? 0x1f this register contains the value of the column of a key detected as valid by the hardwar e. in bypass mode, this register firmware writes directly this register to carry out manual scanning. table 64 : the kcol register msb lsb C C C col.4 col.3 col.2 col.1 col.0 bit symbol function kcol.7 C kcol.6 C kcol.5 C kcol.4 col.4 drive lines bit mapped to corresponding with pins col(4:0). when a key is detected, firmware reads this register to determine column. in bypass (s/w keyscan) mode, firmware writes this register directly. 0x1e = col(0) low, all others high. 0x0f = col(4) low, all others high. 0x1f = col(4:0) all high. kcol.3 col.3 kcol.2 col.2 kcol.1 col.1 kcol.0 col.0 keypad row regi ster (krow): 0xd2 ? 0x3f this register contains the value of the row of a key detected as valid by the hardware. in bypass mode, this register firmware reads directly this register to carry out manual detec tion. table 65 : the krow register msb lsb C C row.5 row.4 row.3 row.2 row.1 row.0 bit symbol function krow.7 C krow.6 C krow.5 row.6 sense lines bit mapped to correspond with pins row(5:0). when key detected, firmware reads this register to determine row. in bypass mode, firmware reads rows and has to determine if there was a key press or not. 0x3e = row(0) low, all others high. 0x1f = row(5) low, all others high. 0x3f = row(5:0) all high. krow.4 row.4 krow.3 row.3 krow.2 row.2 krow.1 row.1 krow.0 row.0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 65 k eypad scan time register (kscan): 0xd3 ? 0x00 this register contains the values of scanning time and debouncing time. table 66 : the kscan register msb lsb dbtime.5 dbtime.4 dbtime.3 dbtime.2 dbtime.1 dbtime.0 sctime.1 sctime.0 bi t symbol function kscan.7 dbtime.5 debounce time in 4ms increments. 1 = 4ms de - bounce time, 0x3f = 252ms, 0x00 = 256ms. key presses and key releases are debounced by this amount of time. kscan.6 dbtime.4 kscan.5 dbtime.3 kscan.4 dbtime.2 kscan.3 dbtime.1 kscan.2 dbtime.0 kscan.1 sctime.1 scan time in ms. 01 = 1ms, 02 = 2ms, 00 = 3ms, 00 = 4ms. time between checking each key during keypad scanning. kscan.0 sctime.0 keypad control/status register (kstat): 0xd4 ? 0x00 this register is used to control the hardware keypad scanning and detection capabilities, as well as the keypad interrupt control and status. table 67 : the kstat register msb lsb C C C C keyclk hwscen keydet kydten bit symbol function kstat.7 C kstat.6 C kstat.5 C kstat.4 C kstat.3 keyclk the current state of the keyboard clock can be read from this bit. kstat.2 hwscen hardware scan enable C when set, the hardware will perform automatic key scanning. when cleared, the firmware must perform the key scanning manually (bypass mode). kstat.1 keydet key detect C when hwscen = 1, this bit is set causing an interrupt that indicates a valid key press was detected and the key location can be read from the keypad column and row registers. when hwscen = 0, this bit is an interrupt which indicates a falling edge on any row input if all row inputs had been high previously (note: multiple key detect interrupts may occur in this case due to the keypad switch bouncing). in all cases, this bit is cleared when read. when hwscen = 0 and the keypad interface 1khz clock is disabled, a key press will still set this bit and cause an interr upt. kstat.0 kydten key detect enable C when set, the keydet bit can cause an interrupt and when cleared the keydet cannot cause an interrupt. keydet can still get set even if the interrupt is not enabled. downloaded from: http:///
73s1210f data sheet ds_1210f_001 66 rev. 1.4 keypad scan time register (ksize): 0xd5 ? 0x00 this register is not applicable when hwscen is not set. unused row inputs shoul d be connected to vdd. table 68 : the ksize register msb lsb C C rowsiz.2 rowsiz.1 rowsiz.0 colsiz.2 colsiz.1 colsiz.0 bit symbol function ksize.7 C ksize.6 C ksize.5 rowsiz.2 defines the number of rows in the keypad. maximum number is 6 given the number of row pins on the package. allows for a reduced keypad size for scanning. ksize.4 rowsiz.1 ksize.3 rowsiz.0 ksize.2 colsiz.2 defines the number of columns in the keypad. maximum number is 5 given the number of column pins on the package. allows for a reduce d keypad size for scanning. ksize.1 colsiz.1 ksize.0 colsiz.0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 67 keypad column ls scan order register (korderl): 0xd6 ? 0x00 in the korderl and korderh registers, column scan order(14:0) is grouped into 5 sets of 3 bits each. each set determines which column (col(4:0) pin) to activate by loading the col umn number into the 3 bits. when in hw_scan_enable mode, the hardware will step through the sets from 1c ol to 5col (up to the number of columns in colsize) and scan the column defined in the 3 bits. to scan in sequential order, set a counting pattern with 0 in set 0, and 1 in set 1,and 2 in set 2, and 3 in set 3, and 4 in set 4. the firmware should update this as part of the interrupt service routine so that the new scan order is loaded prior to the next key being pressed. for example, to scan col(0) first, 1col (2:0) should be loaded with 000b. to scan col(4) fifth, 5col(2:0) should be loaded with 100b. table 69 : the k orderl register msb lsb 3col.1 3col.0 2col.2 2col.1 2col.0 1col.2 1col.1 1col.0 bit symbol function korderl.7 3col.1 column to scan 3 rd (lsbs). korderl.6 3col.0 korderl.5 2col.2 column to scan 2 nd . korderl.4 2col.1 korderl.3 2col.0 korderl.2 1col.2 column to scan 1 st . korderl.1 1col.1 korderl.0 1col.0 keypad column ms scan order register (korderh): 0xd7 ? 0x00 table 70 : the korderh register msb lsb C 5col.2 5col.1 5col.0 4col.2 4col.1 4col.0 3col.2 bit symbol fun ction korderh.7 C korderh.6 5col.2 column to scan 5 th . korderh.5 5col.1 korderh.4 5col.0 korderh.3 4col.2 column to scan 4 th . korderh.2 4col.1 korderh.1 4col.0 korderh.0 3col.2 column to scan 3 rd (msb). downloaded from: http:///
73s1210f data sheet ds_1210f_001 68 rev. 1.4 external interrupt control register (i nt5ctl): 0xff94 ? 0x00 table 71 : the int5ctl register msb lsb pdmux C C C C C kpien kpint bit symbol function int5ctl.7 pdmux power down multiplexer control. int5ctl.6 C int5ctl.5 C int5ctl.4 C int5ctl.3 C int5ctl.2 C int5ctl.1 kpien enables keypad interrupt when set = 1. int5ctl.0 kpint this bit indicates the keypad logic has set key_detect bit and a key location may be read. cleared on read of register. 1.7.14 emulator port the emulator port, consisting of the pins e_rst, e_tclk and e_rxtx, provides cont rol of the mpu through an external in - circuit emulator. the e_tbus[3:0] pins, together with the e_isync/brkrq , add trace capability to the emulator. the emulator port is compatible with the adm51 emulators manufactured by signum systems ?. the signals of the emulator port have weak pull - ups. adding resistor footprints for signals e_rst, e_tclk and e_rxtx on the pcb is recommended. if necessary, adding 10k ? pull - up resistors on e_tclk and e_rxtx and a 3k ? on e_rst will help the emulator operate normally if a problem arises. if code trace capability is needed on this interface, 20pf capacitors ( (to ground) need t o be added to allow the trace function capability to run properly. these capacitors should be attached to the tbus0:3 and isbr signals. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 69 1.7.15 smart card interface function the 73s1210f integrates one iso - 7816 (t=0, t=1) uart, one complete icc electrical interface as well as an external smart card interface to allow multiple smart cards to be connected us ing the teridian 8010 family of interface devices. figure 14 shows the simplified block diagram of the card circuitry (uart + interfaces), with detail of dedicated xram registers. figure 14 : smart card interface block diagram card interrupts are managed through two dedicated registers: scie (interrupt enable to define which interrupt is enabled) and scint (interrupt status). they allow the firmware to determine the source of an interrupt, that can be a card insertion / removal, card power fault, or a transmis sion (tx) or reception (rx) event / fault. it should be noted that even when card clock is disabled, an icc inter rupt can be generated direct mode card insertion activation / deactivation sequencer vcc buffer / level shifter rst buffer / level shifter clk i/o buffer / level shifter c4 buffer / level shifter c8 buffer / level shifter vcc card generation icc event icc pwr_event i/o icc#1 i/oext. icc clk icc clkext. icc card clock management 7.2mhz scclk/ scsclk pres serial uart internal icc interface scsel uart t=0 t=1 rlength ststo atrmsb/lsb bgt/egt srxdata srxctl stxdata stxctl scprtcol scctl fdreg sbytectl sparctl card interrupt management scint scie external icc interface bypass mode xram registers vccctl/ vcctmr scclk/scsclk timers 2-byte tx fifo 2-byte rx fifo card and mode selection tx rx scdir scectl bgt0/1/2/3/ cwt0/1 sio sclk scclk scsclk downloaded from: http:///
73s1210f data sheet ds_1210f_001 70 rev. 1.4 on a card insertion / removal to allow power saving modes. card insertion / removal is generated from the respective card switch detection inputs (whose polarity is programmable). the built - in icc interface has a linear regulator (v cc generator) capable of driving 1.8, 3.0 and 5.0v smart cards in accordance with the iso 7816 - 3 and emv4.1 standards. this converter uses the v p (5.5v nominal) input supply source. see the power supply management section above for more detail. auxiliary i/o lines c4 and c8 are only provided for the built - in interface. if support for the auxiliary lines is necessary for the external smart card interface, they need to be handled manually through the u sr gpio pins. the external 73s8010x devices directly connect the i/o (sio) and clock (s clk) signals and control is handled via the i 2 c interface. figure 15 shows how multiple 8010 devices can be connected to the 73s1210f. 73 s 1210 f 73 s 8010 73 s 8010 sc 3 sc 2 73 s 8010 sc (n) sc 1 int 3 sda scl int scl sda int scl sda int scl sda sad (0:2) sad (0:2) sad (0:2) i/o rst clk c4 c8 vpc pres pres pres iouc iouc iouc xtalin xtalin xtalin gnd pres vpc pres sio sclk vcc figure 15 : external smart card interface block diagram downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 71 1.7.15.1 iso 7816 uart an embedded iso 7816 (hardware) uart is provided to control communications between a smart card and the 73s1210f mpu. the uart can be shared between the one built - in icc interface and the extern al icc interface. selection of the desired interface is made by register scsel . control of the external interface is handled by the i 2 c interface for any external 73s8010x device. the following is a list of features for the iso 7816 uart: ? two- byte fifo for temporary data storage on both tx and rx data. ? parity checking in t=0. this feature can be enabled/disabled by firmware. parity error reporting to firmware and break generation to icc can be controlled independently. ? parity error generation for test purposes. ? retransmission of last byte if icc indicates t=0 parity error. this f eature can be enabled/disabled by firmware. ? deletion of last byte received if icc indicates t=0 parity error. this f eature can be enabled/disabled by firmware. ? crc/lrc genera tion and checking. crc/lrc is automatically inserted into t=1 data stream by t he hardware. this feature can be enabled/disabled by firmware. ? support baud rates: 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware control (assuming 12mhz crystal) with various f/d settings. ? firmware manages f/d. all f/d combinations are supported in which f/d is di rectly divisible by 31 or 32 (i.e. f/d is a multiple of either 31 or 32). ? flexible etu clock generation and control. ? detection of convention (direct or indirect) character ts. this affects both polarity and order of bits in byte. convention can be overridden by firmware. ? supports wtx timeout with an expanded wait time counter (28 bits). ? a bypass mode is provided to bypass the hardware uart in order for the software to emulate the uart (for non - standard operating modes). in such a case, the i/o line value is reflected in sfr scctl or scectl respectively for the built - in or external interfaces. this mode is appropriate for some synchronous and non t=0 / t=1 cards. the single integrated smart card uart is capable of supporting t=0 and t=1 cards in har dware therefore offloading the bit manipulation tasks from the firmware. the embedded firmwar e ins tructs the hardware which smart card it should communicate with at any point in time. fir mware reconfigures the uart as required when switching between smart cards. when the 73s1210f has transmitted a message with an expected response, the firmware should not switch the uart to another s mart card until the first smart card has responded. if the smart card responds while another smart card is selected, that first smart cards response will be ignored. downloaded from: http:///
73s1210f data sheet ds_1210f_001 72 rev. 1.4 1.7.15.2 answer to reset processing a card insertion event generates an interrupt to the firmware, which is then responsibl e for the configuration of the electrical interface, the uart and activation of the card. t he activation sequencer goes through the power up sequence as defined in the iso 7816 - 3 specification. an asynchronous activation timing diagram is shown in figure 16. after the card reset is de - asserted, the firmware instructs the hardware to look for a ts byte that begins the atr response. if a response is not provided within the pre - programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instruct ing the 73s1210f to begin a deactivation sequence. once commanded, the deactivation sequencer goes through the power down sequence as defined in the iso 7816 - 3 specification. if an atr response is received, the hardware looks for a ts byte that determines direct/inverse convention. the hardware handles the indirect convention conversion such that the embedded firmware only receives direct convention. this feature can be disabled by firmware within sbytectl register. parity checking and break generation is performed on the ts byte unless disabled by firmware. if during the card session, a card removal, over - current or other error event is detected, the hardware will automatically perform t he deactivation sequence and then generate an interrupt to the firmware. the firmware can then perf orm any other error handling required for proper system operation. smart card rst, i/o and clk, c4, c8 shall be low before the end of the deactivation sequence. figure 17 shows the timing for a deactivation sequence. vccsel bits vcc vccok bit rstcrd bit rst clk io t1 t2 t3 t4 t5 tto see note atr starts t4 selsc bits t1: se lsc.1 bit set (selects internal icc interface) and a non - zero value in vccsel bits (calling for a value of vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 i s the time for vcc to rise to acceptable level, declared as vcc ok (bit vccok gets set). this time depends on filter capacitor value and card icc load. tto: the time allowed for vcc to rise to vcc ok status after setting of the vccsel bits. this time is generated by the vcctmr counter. if vcc ok is not set, (bit vccok) at this time, a deactivation will be initiated. vccsel bits are not automatically cleared. the firmware must clear the vccsel bits before starting a new activation. t2: time from vcctmr timeout and vcc ok to io reception (high), typi cally 2 - 3 clk cycles if rdyst = 0. if rdyst = 1, t2 starts when vccok = 1. t3: time from io = high to clk start, typically 2 - 3 clk cycles. t4: time allowed for start of clk to de - assertion of rst. programmable by the rlength register. t5: time allowed for atr timeout, set by the ststo register. note: if the rstcrd bit is set, rst is asserted (low). upon clear ing rstcrd bit, rst will be de - asserted after t4. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 73 figure 16 : asynchronous activation sequence timing vcc io rst clk t1 t2 t3 t4 t5 firmware sets vccsel to 00 cmdvccnb t5 delay or card event t1: time after either a card event occurs or firmware sets the vccsela and vccselb bits to 0 (see t5, vccoff_tmr) occurs until rst is asserted low. t2: time after rst goes low until clk stops. t3: time after clk stops until io goes low. t4: time after io goes low until vcc is powered down. t5: delayed vcc off time (in etus per vccoff_tmr bits). only in effect due to firmware deactivation. figure 17 : deactivat ion sequence 1.7.15.3 data reception/transmission when a 12mhz crystal is used, the smart card uart will generate a 3.69mhz (default ) clock to both smart card interfaces. this will allow approximately 9600bps (1/etu) communi cation during atr (iso 7816 default). as part of the pps negotiation between the smart card and the reader, the fi rmware may determine that the smart card parameters f & d may be changed. after this negotiati on, the firmware may change the etu by writing to the sfr f dreg to adjust the etu and clk. the firmware may also change the smart card clock frequency by writing to the sfr scclk ( sceclk for external interface). independent clock frequency control is provided to each smart card interface. clock s top high or clock stop low is supported in asynchronous mode. figure 18 shows the etu and clk control circuits. the firmware determines when clock stop is supported by the smart card and when it is appropriate to go into that mode (and when to come out of it). the smart card uart is clocked by the same clock that is provided to the selected smart card. the transition between smart card clocks is handled in hardware to eli minate any glitches for the uart during switchover. the external smart card c lock is not affected when switching the uart to communicate with the internal smart card. downloaded from: http:///
73s1210f data sheet ds_1210f_001 74 rev. 1.4 pll etu divider 12 bits fi decoder div by 2 etuclk clk div by 2 sclk pre-scaler 6 bits pre-scaler 6 bits f/d register scclk(5:0) scsclk(5:0) msclk msclke mclk = 96mhz fdreg(3:0) fdreg(7:4) 9926 1/744 3.69m 1/13 7.38m 7.38m 3.69m 7.38m defaults in italics scsel(3:2) 1/13 sync center edge figure 18 : smart card clk and et u generation there are two, two - byte fifos that are used to buffer transmit and receive data. during a t=0 processing, if a parity error is detected by the 73s1210f during message reception, an error signal (b reak) will be generated to the smart card. the byte received will be discarded and the firmware notif ied of the error. break generation and receive byte dropping can be disabled under firmware control. during the transmission of a byte, if an error signal (break) is detected, the last by te is retransmitted again and the firmware notified. retransmission can be disabled by firmware. when a correct byte is received, an interrupt is generated to the firmware, which then reads the byte from the receive fi fo. receive overruns are detected by the hardware and reported via an interrupt. during transmission of a message, the firmware will write bytes into the transmit fifo. the hardware will send them to the smart card. when the last byte of a message has been written, the firmware will need to set the lasttx bit in the stxctl sfr. this will cause the hardware to insert the crc/lrc if in a t=1 protocol mode. crc/lrc generation/checking is only provided during t=1 processing. firmware will need to ins truct the smart funct ion to go into receive mode after this last transmit data byte if it expects a response from the smart card. at the end of the smart card response, the firmware will put the interfac e back into transmit mode if appropriate. the hardware can check for the following card - related timeouts: ? character waiting time (cwt) ? block waiting time (bwt) ? initial waiting time (iwt) the firmware will load the wait time with the appropriate value for the operating mode at the appropriate time. figure 19 shows the guard, block, wait and atr time definitions. if a timeout occurs, an interrupt will be generated and the firmware can take appropriate recovery steps. support is provi ded for adding additional guard times between characters using the extra guard time register ( egt ), and between the last byte received by the 73s1210f and the first byte transmitted by the 73s1210f using the block guard time register ( bgt ). other than the protocol checks described above, the firmware is responsible for all protocol checking and error recovery. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 75 > egt < wwt char 1 char 2 char n+1 char n+2 char n+3 block1 block2 > bwt < cwt reception transmission t = 1 mode char 1 char 2 char n rst tsto(7:0) atrto(15:0) vcc_ok rlen(7:0) char 1 char 2 char n atr timing parameters iwt(15:0) bgt(4:0) tx t = 0 mode io egt (by seting last_txbyte and tx/rxb=0 during char n, rx mode will start after last tx byte) wwt is set by the value in the bwt registers. figure 19 : guard, block, wait and atr time definitions 1.7.15.4 bypass mode it is possible to bypass the smart card uart in order for the firmware to support non - t=0/t=1 smart cards. this is called bypass mode. in this mode the embedded firmware will c ommunicate directly with the selected smart card and drive i/o during transmit and read i/o during receive in order to communicate with the smart card. in this mode, atr processing is under firmware control . the firmware must sequence the interface signals as required. firmware must perform ts processing, par ity checking, break generation and crc/lrc calculation (if required). 1.7.15.5 synchronous operation mode the 73s1210f supports synchronous operation. when sync mode is selected for either interface, the clk signal is generated by the etu counter. the values in c, scclk , and sceclk must be set to obtain the desired sync clk rate. there is only one etu counter and therefore, in sync mode, the interface must be selected to obtain a smart card clock signal. in sync mode, i nput data is sampled on the rise of clk, and output data is changed on the fall of clk. downloaded from: http:///
73s1210f data sheet ds_1210f_001 76 rev. 1.4 special notes regarding synchronous mode operation when the scisyn or scesnc bits ( sprtcol , bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. the following requirements are to be noted: 1. the source for the smart card clock (clk or sclk) is the etu counter. o nly the actively selected interface can have a running synchronous clock. in contrast, an unselected interface may have a running clock in the asynchronous mode of operation. 2. the control bits clklvl, sclklvl, clkoff, and sclkoff are functional in synchr onous mod e. when the clkoff bit is set, it will not truncate either the logic low or l ogic high period when the (stop at) level is of opposite polarity. the clk/sclk signal will complete a corr ect logic low or logic high duty cycle before stopping at the selected level. the clk start is a result of the falling edge of the clkoff bit. setting clock to run when it is stopped low will result in a half period of low before going high. setting clock to run when it is stopped high will result in the clock goi ng low immediately and then running at the selected rate with 50% duty cycle (within the limitations of t he etu divisor value). 3. the rlen(7:0) is configured to count the falling edges of the etu clock (clk or sc lk) after it has been loaded with a value from 1 to 255. a value of 0 disables the counting function and rlen functions such as i/o source selection (i/o signal bypasses the fifos and is controlled by the scclk / sceclk sfrs). when the rlen counter reaches the max (loaded) value, it sets the waitto interrupt ( scint , bit 7), which is maskable via wtoien ( scie , bit 7). it must be reloaded in order to start the counting/clocking process again. this allows the processor to sel ect the number of clk cycles and hence, the number of bits to be read or written to/from the card. 4. the fifo is not clocked by the first clk (falling) edge resulting from a clk off de - assertion (a clock start event) when the clk was stopped in the high state and rlen has been loaded but not yet clocked. 5. the state of the pin io or sio is sampled on the rising edge of clk/sclk and stored in bit 5 of the scctl / scectl register. 6. when rlen = max or 0 and i2cmode = 1 ( stxctl , b7), the io or sio signal is directly controlled by the data and direction bits in the respective scctl and scectl register. the state of the data in the tx fifo is bypassed. 7. in the sprtcol register, bit 6 (mode9/8b) becomes active. when set, the rxdata fifo wi ll read nine - bit words with the state of the ninth bit being readable in srxctl , bit 7 (b9dat). the rxdav interrupt will occur when the ninth bit has been clocked in (rising edge of clk or sc lk). 8. care must be taken to clear the rx and tx fifos at the start of any transacti on. the user shall read the rx fifo until it indicates empty status. reading the tx fifo twic e will reset the input byte pointer and the next write to the tx fifo will load the byte to the first out position. note that the bit pointer (serializer/deserializer) is reset to bit 0 on any change of the tx/rxd bit. special bits that are only active for sync mode include: srxctl , b7 bit9dat, sprtcol , b6 mode9/8b, stxctl , b7 i2cmode , and the definition of scint , b7, which was waitto, becomes rlenint interrupt, and scie , b7, which was wtoien, becomes rlenien. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 77 vcc vccok rstcrd rst clk io t1 t2 t3 t4 tto vccsel bits t1: the time from setting vccsel bits until vccok = 1. tto: the time from setting vccsel bits until vcctmr times out. at t1 (if rdyst = 1) or tto (if rdyst = 0), activation starts. it is suggested to have rdyst = 0 and use the vcctmr interrupt to let mpu know when sequence is starting. t2: time from start of activation (no external indication) until io goes into recept ion mode (= 1). this is approximately 4 scclk (or sceclk ) clock cycles. t3: minimum one half of etu period. t4: etu period. note that in sync mode, io as input is sampled on the rising edge of clk. io changes on the falling edge of clk, either from the card or from the 73s1210f. the rst signal to the card is directly controlled by the rstcrd bit (non - inverted) via the mpu and is shown as an example of a possible rst pattern. figure 20 : synchronous activation io reception on rst clk clkoff clklvl rlength interrupt rlength count rlenght = 1 tx / rxb mode bit ( tx = '1') 1 . clear clkoff after card is in reception mode . 2 . set rst bit . 3 . interrupt is generated when rlength counter is max . 4 . read and clear interrupt . 5 . clear rst bit . 6 . toggle tx / rxb to reset bit counter . 7 . reload rlength counter . count max 1 2 4 7 5 t1 . clk wll start at least 1/ 2 etu after clkoff is set low when clklvl = 0 t1 3 6 figure 21 : example of sync mode operation: generating/reading atr signals downloaded from: http:///
73s1210f data sheet ds_1210f_001 78 rev. 1.4 rlength count - was set for length of atr clk io rlength interrupt clk stop clk stop level io bit iodir bit tx / rx mode bit tx = '1' data from card - end of atr data from tx fifo rlength count max 1 . interrupt generated when rlength counter is max . 2 . read and clear interrupt . 3 . set clk stop and clk stop level high in interrupt routine . 4 . set tx / rx bit to tx mode . 5 . reload rlength counter . 6 . set io bit low and iodir = output . since rlen =( max or 0 ) and tx / rx =1 , io pin is controlled by io bit . 7 . clear clk stop and clk stop level . note: data in tx fifo should not be empty here . start bit synchronous clock start / stop mode style start bit procedure . this procedure should be used to generate the start bit insertion in synchronous mode for synchronous clock start / stop mode protocol . rlen =0 rlen =1 2 1 3 7 6 5 6 4 figure 22 : creatio n of synchronous clock start/stop mode start bit in sync mode rlength count (rlength = 9) clk io rlength interrupt clk stop clk stop level io bit iodir bit tx/rx mode bit tx = '1' i2cmode = 1: data to/from card i2cmode = 0: data from tx fifo i2cmode = 1:ack bit (to/from card) i2cmode = 0: data from tx fifo rlength count max 1. interrupt generated when rlength counter is max. 2. read and clear interrupt. 3. set clk stop and clk stop level high. 4. set io bit low and iodir = output. 5. set tx/rx bit to tx mode. 6. reload rlength counter. 7. set io bit high and iodir = output. 8. clear clk stop and clk stop level. note: data in tx fifo should not be empty here. stop bit tx/rx mode synchronous clock start/stop mode stop bit procedure. this procedure should be used to generate the stop bit in synchronous mode. syckst is bit 7 of stxctl register. 1 2 4 3 5 6 8 7 figure 23 : creation of synchronous clock start/stop mode stop bit in sync mode downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 79 rlength count rlength = 9 clk io rlength interrupt rx data tx/rx mode bit tx = '1' data from card (bit 8) data from card (bit 1) rlength count max rlen=9 protection bit (bit 9) rx fifo (data from card is ready for cpu read) protection bit is ready for cpu read rlen=8 rlen=0 rlen =1 protection bit data (bit 9) 1._ interrupt generated when rlength counter is max 2._ read and clear interrupt 3._ reload rlength counter rlength count rlength = 9 rlength count max rlen=9 rlen=8 rlength interrupt clk clk stop clk stop level = 0 1._ interrupt generated when rlength counter is max 2._stop clk after the last byte and protection bit stop clk after receiving the last byte and protection bit. receive data in 9 bit mode figure 24 : operation of 9 - bit mode in sync mode synchronous card operation is broken down into three primary types. these are commonly r eferred to as 2- wire, 3 - wire and i2c synchronous cards. each card type requires different control and timing and therefo re requires different algorithms to access. teridian has created an application note to provide detailed algorithms for each card type. refer to the application note titled 73s12xxf synchronous card design application note . downloaded from: http:///
73s1210f data sheet ds_1210f_001 80 rev. 1.4 1.7.15.6 smart card sfrs smart card select register (scsel): 0xfe00 ? 0x00 the smart card select register is used to determine which smart card interface is using the iso uart. the internal smart card has integrated 7816 - 3 compliant sequencer circuitry to drive an external smart card interface. the external smart card interface relies on 73s8010 parts to generate the iso 7816 - 3 compatible signals and sequences. multiple 73s8010 devices can be connected to the external smart card interface. table 72 : the scsel reg ister msb lsb C C C C selsc.1 selsc.0 bypass C bit symbol function scsel.7 C scsel.6 C scsel.5 C scsel.4 C scsel.3 selsc.1 select smart card interface - these bits select the interface that is using the is0 uart. these bits do not activate the interface. activation is performed by the vccctl register. 00 = no smart card interface selected. 01 = external smart card interface selected (using sclk, sio). 1x = internal smart card interface selected. scsel.2 selsc. 0 scsel.1 bypass 1 = enabled, 0 = disabled. when enabled, iso uart is bypassed and the i/o line is controlled via the scctl and scectl registers. scsel.0 C downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 81 smart card interrupt register (scint): 0xfe01 ? 0x00 when the smart card interrupt is asserted, the firmware can read this register t o determine the actual cause of the interrupt. the bits are cleared when this register is read. each int errupt can be disabled by the smart card interrupt enable register. error processing must be handled by the fi rmware. this register relates to the interface that is active C see the scsel register (above). table 73 : the scint register msb lsb waitto c rdevt vcctmri rxdav txevt txsent txerr rxerr bit symbol function scint.7 waitto wait timeout - an atr or card wait timeout has occurred. in sync mode, this interrupt is asserted when the rlen counter (it advances on falling edges of clk/etu) reaches the loaded (max) value. this bit is cleared when the scint register is read. when running in synchronous clock stop mode, this bit becomes rlenint interrupt (set when the rlen counter reaches the terminal count). scint.6 crdevt card event - a card event is signaled via pin detcard either when the card was inserted or removed (read the crdctl register to determine card presence) or there was a fault condition in the interface circuitry. this bit is functional even if the smart card logic clock is disabled and when the pwrdn bit is set. this bit is cleared when the scint register i s read. scint.5 vcctmri vcc timer - this bit is set when the vcctmr times out. this bit is cleared when the scint register is read. scint.4 rxdav rx data available - data was received from the smart card because the rx fifo is not empty. in bypass mode, this interrupt is generated on a falling edge of the smart card i/o line. after receiving this interrupt in bypass mode, firmware should disable it until the firmware has received the entire byte and is waiting for the next start delimiter. this bit is cleared when there is no rx data available in the rx fifo. scint.3 txevnt tx event - set whenever the txemty or txfull bits are set in the srxctl sfr. this bit is cleared when the stxctl register is read. scint.2 txsent tx sent - set whenever the iso uart has successfully transmitted a byte to the smart card. also set when a crc/lrc byte is sent in t=1 mode. will not be set in t=0 when a break is detected at the end of a byte (when break detection is enabled). this bit is cleared when the scint register is read. scint.1 txerr tx error - an error was detected during the transmission of data to the smart card as indicated by either breakd or txundr bit being set in the stxctl sfr. additional information can be found in that register description. this bit is cleared when the stxctl regi ster is read. scint.0 rxerr rx error - an error was detected during the reception of data from the smart card. additional information can be found in the srxctl register. this interrupt will be asserted for rxovrr, or rx parity error events. this bit is cleared when the srxctl register is read. downloaded from: http:///
73s1210f data sheet ds_1210f_001 82 rev. 1.4 smart card interrupt enable register (scie): 0xfe02 ? 0x00 when set to 1, the respective condition can cause a smart card interrupt. when set t o a 0, the respective condition cannot cause an interrupt. when disabled, the respective bit in the smart card interrupt register can still be set, but it will not interrupt the mpu. table 74 : the scie register msb lsb wtoien cdeven vtmren rxdaen txeven txsnten txeren rxeren bit symbol function scie.7 wtoien wait timeout interrupt enable - enable for atr or wait timeout interrupt. in sync mode, function is rlien (rlen = max.) interrupt enable. scie.6 cdeven card event interrupt ena ble. scie.5 vtmren vcc timer interrupt enable. scie.4 rxdaen rx data available interrupt enable. scie.3 txeven tx event interrupt enable. scie.2 txsnten tx sent interrupt enable. scie.1 txeren tx error interrupt enable. scie.0 rxeren rx error interru pt enable. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 83 smart card v cc control/status register (vccctl): 0xfe03 ? 0x00 this register is used to control the power up and power down of the integrated smart card interface. it is used to determine whether to apply 5v, 3v, or 1.8 to the smart card. perform the v oltage selection with one write operation, setting both vccsel.1 and vccsel.0 bits simultaneously. the vddflt bit (if enabled) will provide an emergency deactivation of the internal smart card slot. see t he vdd fault detect function section for more detail. table 75 : the vccctl register msb lsb vccsel.1 vccsel.0 vddflt rdyst vccok C C scpwrdn bit symbol function vccctl.7 vccsel.1 setting non - zero value for bits 7,6 will begin activation sequence with target vcc as given below: state vccsel.1 vccsel.0 vcc 1 0 0 0v 2 0 1 1.8v 3 1 0 3.0v 4 1 1 5v a card event or vccok going low will initiate a deactivation sequence. when the deactivation sequence for rst, clk and i/o is complete, v cc will be turned off. when this type of deactivation occurs, the bits must be reset before initiating another activation. vccctl.6 vccsel.0 vccctl.5 vddflt when there is a vdd fault event, this bit will be set = 0. this causes vccsel.1 and vccsel.0 bits to be immediately set = 0 to begin deactivation. vccctl.4 rdyst if this bit is set = 1, the activation sequence will start when bit vcco k is set = 1. if not set, the deactivation sequence shall start when the vcctmr times out. vccctl.3 vccok (read only). indicates that v cc output voltage is stable. vccctl.2 C vccctl.1 C vccctl.0 scpwrdn this bit controls the power - off mode of the 73s1210f circuit. 1 = power off, 0 = normal operation. when in power down mode, v dd = 0v. v dd can only be turned on by pressing the on/off switch or by application of 5v to v bus . if v bus power is available and scpwrdn bit is set, it has no effect until v bus is removed and v dd will shut off. downloaded from: http:///
73s1210f data sheet ds_1210f_001 84 rev. 1.4 v cc stable timer register (vcctmr): 0xfe04 ? 0x0f a programmable timer is provided to set the time from activation start (setting the vccsel.1 and vccsel.0 bits to non - zero) to when vcc_ok is evaluated. vcc_ok must be true at the end of this timers programmed interval (tto in figure 16 ) in order for the activation sequence to continue. if vcc_ok is not true and the end of the interval (tto), the card event interrupt will be set , and a deactivation sequence shall begin including clearing of the vccsel bits. table 76 : the vcctmr register msb lsb offtmr.3 offtmr.2 offtmr.1 offtmr.0 vcctmr.3 vcctmr.2 vcctmr.1 vcctmr.0 bit symbol function vcctmr .7 offtmr.3 vcc off timer - the bits set the delay (in number of etus) for deactivation after the vccsel.1 and vcc sel.0 have been set to 0. the time value is a count of the 32768hz clock and is given by tto = offtmr(7:4) * 30.5 s. this delay does not affect emergency deactivations due to vdd fault or card events. a value of 0000 results in no additional delay. vcctmr .6 offtmr.2 vcctmr .5 offtmr.1 vcctmr .4 offtmr.0 vcctmr.3 vcctmr.3 vcc timer - vccok must be true at the time set by the value in these bits in order for the activation sequence to continue. if not, the vccsel bits will be cleared. the time value is a count of the 32768hz clock and is given by tto = vcctmr(3:0) * 30.5s. a value of 0000 results in no timeout, not zero time, and activation requires that rdyst is set and rdy goes high. vcctmr .2 vcctmr.2 vcctmr .1 vcctmr.1 vcctmr .0 vcctmr.0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 85 card status/control register (crdctl): 0xfe05 ? 0x00 this register is used to configure the card detect pin (detcard) and monitor car d detect status. this register must be written to properly configure debounce, detect_polarity (= 0 or = 1), and the pull - up/down enable before setting cdeten. the card detect logic is functional even without smart card logic clock. wh en the pwrdn bit is set = 1, no debounce is provided but card presence is operable. table 77 : the crdctl register msb lsb deboun cdeten C C detpol puenb pden cardin bit symbol function crdctl .7 deboun debounce - when set = 1, this will enable hardware debounce of the card detect pin. the debounce function shall wait for 64ms of stable card detect assertion before setting the cardin bit. this counter/timer uses the keypad clock as a source of 1khz signal. de - assertion of the cardin bit is immediate upon de - assertion of the card detect pin(s). crdctl .6 cdeten card detect enable - when set = 1, activates card detection input. default upon power - on reset is 0. crdctl .5 C crdctl .4 C crdctl.3 detpol detect polarity - w hen set = 1, the detcard pin shall interpret a logic 1 as card present. crdctl .2 puenb enable pull - up current on detcard pin (active low). crdctl .1 pden enable pull - down current on detcard pin. crdctl .0 cardin card inserted - (read only). 1 = card inserted, 0 = card not inserted. a change in the value of this bit is a card event. a read of this bit indicates whether smart card is inserted or not inserted in conjunction with the detpol setting. downloaded from: http:///
73s1210f data sheet ds_1210f_001 86 rev. 1.4 tx control/status register (stxctl): 0xfe06 ? 0x00 th is register is used to control transmission of data to the smart card. some control and some status bits are in this register. table 78 : the stxctl register msb lsb i2cmode C txfull txemty txundr lasttx tx/rxb breakd bit symbol function stxctl.7 i2cmode i2c mode - when in sync mode and this bit is set, and when the rlen count value = max or 0, the source of the smart card data for io pin (or sio pin) w ill be connected to the io bit in scctl (or scectl ) register rather than the tx fifo. see the description for the protocol mode register for more detail. stxctl.6 C stxctl.5 txfull tx fifo is full. additional writes may corrupt the contents of the fif o. this bit it will remain set as long as the tx fifo is full. generates a tx _event interrupt upon going full. stxctl.4 txemty 1 = tx fifo is empty, 0 = tx fifo is not empty. if there is dat a in the tx fifo, the circuit will transmit it to the smart card if in transmit mode. in t=1 mode, if the lasttx bit is set and the hardware is configured to transmit the crc/lrc, the txemty will not be set until the crc/lrc is transmitt ed. in t=0, if the lasttx bit is set, txemty will be set after the last word has been successfully transmitted to the smart card. generates a txevnt interrupt upon going empty. stxctl.3 txundr tx underrrun - (read only) asserted when a transmit under - run condition has occurred. an under - run condition is defined as an empty tx fifo when the last data word has been successfully transmitted to the smart card and the lasttx bit was not set. no special processing is performed by the hardware if this condition occurs. cleared when read by firmware. this bit generates a txerr interrupt. stxctl.2 lasttx last tx byte - set by firmware (in both t=0 and t=1) when the last byte in the current message has been written into the transmit fifo. in t=1 mode, the crc/lrc will be appended to the message. should be set after the last byte has been written into the transmit fifo. should be cleared by firmware before writing first byte of next message into the transmit fifo. used in t=0 to determine when to set txemty . stxctl.1 tx/rxb 1 = transmit mode, 0 = receive mode. configures the hardware to be receiving from or transmitting to the smart card. determines which counters should be enabled. this bit should be set to receive mode prior to switching to another interface. setting and resetting this bit shall initialize the crc logic. if lasttx is set, this bit can be reset to rx mode and uart logic will automatically change mode to rx when tx operation is completed (tx_empty = 1). stxctl.0 breakd break detected - (read only) 1 = a break has been detected on the i/o line indic ating that the smart card detected a parity error. cleared when read. this bit generates a txerr interrupt. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 87 stx data register (stxdata): 0xfe07 ? 0x00 table 79 : the stxdata register msb lsb stxdat.7 stxdat.6 stxdat.5 stxdat.4 stxdat.3 stxdat.2 stxdat.1 stxdat.0 bit function stxdata.7 data to be transmitted to smart card. gets stored in the tx fifo and then ext racted by the hardware and sent to the selected smart card. when the mpu reads this register, the byte pointer is changed to effectively read out the data. thus, two reads will always result in an empty fifo condition. the contents of the fifo regist ers are not cleared, but will be overwritten by writes. stxdata.6 stxdata.5 stxdata.4 stxdata.3 stxdata.2 stxdata.1 stxdata.0 srx control/status register (srxctl): 0xfe08 ? 0x00 this register is used to monitor reception of data from the smart card. table 80 : the srxctl register msb lsb bit9dat C lastrx crcerr rxfull rxemty rxovrr paritye bit symbol function srxctl.7 bit9dat bit 9 data - when in sync mode and with mode9/8b set, this bit will contain the data on io (or sio) pin that was sampled on the ninth clk (or sclk) rising edge. this is used to read data in synchronous 9 - bit formats. srxctl.6 C srxctl.5 lastrx last rx byte - user sets this bit during the reception of the last byte. when byte is received and this bit is set, logic checks crc to match 0x1d0f (t =1 mode) or lrc to match 00h (t=1 mode), otherwi se a crc or lrc error is asserted. srxctl.4 crcerr (read only) 1 = crc (or lrc) error has been detected. srxctl.3 rxfull (read only) rx fifo is full. status bit to indicate rx fifo is f ull. srxctl.2 rxemty (read only) rx fifo is empty. this is only a status bit and does not generate an rx interrupt. srxctl.1 rxovrr rx overrun - (read only) asserted when a receive - over - run condition has occurred. an over - run is defined as a byte was received from the smart card when the rx fifo was full. invalid data may be in the receive fifo. firmware should take appropriate action. cleared when read. additional writes to the rx fifo are discarded when a rxovrr occurs until the overrun condition is cleared. will generate an rxerr interrupt. srxctl.0 paritye par ity error - (read only) 1 = the logic detected a parity error on incoming data from the smart card. cleared when read. will generate an rxerr interrupt. downloaded from: http:///
73s1210f data sheet ds_1210f_001 88 rev. 1.4 srx data register (srxdata): 0xfe09 ? 0x00 table 81 : the srxdata register msb lsb srxdat.7 srxdat.6 srxdat.5 srxdat.4 srxdat.3 srxdat.2 srxdat.1 srxdat.0 bit function srxdata.7 (read only) data received from the smart card. data received from the smart card gets stored in a fifo that is read by the firmware. srxdata .6 srxdata.5 srxdata.4 srxdata.3 srxdata.2 srxdata.1 srxdata.0 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 89 smart card control register (scctl): 0xfe0a ? 0x21 this register is used to monitor reception of data from the smart card. table 82 : the scctl register ms b lsb rstcrd C io iod c8 c4 clklvl clkoff bit symbol function scctl.7 rstcrd 1 = asserts the rst (set rst = 0) to the smart card interface, 0 = d e - assert the rst (set rst = 1) to the smart card interface. can be used to extend rst to the smart c ard. refer to rlength register description. this bit is operational in all modes and can be used to extend rst during activation or perform a warm reset as required. in auto - sequence mode, this bit should be set = 0 to allow the sequencer to de - assert rst per the rlength parameters. in sync mode (see the sprtcol register) the sense of this bit is non - inverted, if set = 1, rst = 1, if set = 0, rst = 0. rlen has no effect on reset i n sync mode. scctl.6 C scctl.5 io smart card i/o. read is state of i/o signal (caution, this signal is not synchronized to the mpu clock). in bypass mode, write value is state of signal on i/o. in sync mode, this bit will contain the value of i/o pin on t he latest rising edge of clk. scctl.4 iod smart card i/o direction control bypass mode or sync mode. 1 = input (default), 0 = output. scctl.3 c8 smart card c8. when c8 is an output, the value written to this bit will appear on the c8 line. the value read when c8 is an output is the value stored in the register. when c8 is an input, the value read is the value on the c8 pin (caution, this signal is not synchronized to the mpu clock). when c8 is an input, the value written will be stored in the register but not presented to the c8 pin. scctl.2 c4 smart card c4. when c4 is an output, the value written to this bit will appear on the c4 line. the value read when c4 is an output is the value stored in the register. when c4 is an input, the value read is the value on the c4 pin (caution, this signal is not synchronized to the mpu clock). when c4 is an input, the value written will be stored in the register but not presented to the c4 pin. scctl.1 clklvl 1 = high, 0 = low. if clkoff is set = 1, the clk to smart card wil l be at the logic level indicated by this bit. if in bypass mode, this bit directly c ontrols the state of clk. scctl.0 clkoff 0 = clk is enabled. 1 = clk is not enabled. when asserted, the clk will stop at the level selected by clklvl. this bit has no effect if in bypass mode. downloaded from: http:///
73s1210f data sheet ds_1210f_001 90 rev. 1.4 external smart card control register (scectl): 0xfe0b ? 0x00 this register is used to directly set and sample signals of external smart c ard interface. there are three modes of asynchronous operation, an automatic sequence mode, and bypass mode. clock stop per the iso 7816 - 3 interface is also supported but firmware must handle the protocol for sio and sclk for i 2 c clock stop and start. control for reset (to make rst signal), activation control, voltage select, etc. should be handled via the i 2 c interface when using external 73s8010 devices. usr(n) pins shall be used for c4, c8 functions if necessary. table 83 : the scectl register msb lsb C C sio siod C C sclklvl sclkoff bit symbol function scectl.7 C scectl.6 C scectl.5 sio external smart card i/o. bit when read indicates state of pin sio for si od = 1 (caution, this signal is not synchronized to the mpu clock), when written, sets the state of pin sio for siod = 0. ignored if not in bypass or sync modes. in sync mode, this bit will contain the value of io pin on the latest rising edge of sclk. scectl.4 siod 1 = input, 0 = output. external smart card i/o direction control. ignored i f not in bypass or sync modes. scectl.3 C scectl.2 C scectl.1 sclklvl sets the state of sclk when disabled by sclkoff bit. if in bypass mode, this bit directly controls the state of sclk. scectl.0 sclkoff 0 = sclk enabled, 1 = sclk disabled. when disabled, sclk l evel is determined by sclklvl . this bit has no effect if in bypass mode. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 91 c4/c8 data direction register (scdir): 0xfe0c ? 0x00 this register determines the direction of the internal interface c4/c8 lines. a fter reset, all signals are tri - stated. tab le 84 : the scdir register msb lsb C C C C c8d c4d C C bit symbol function scdir.7 C scdir.6 C scdir.5 C scdir.4 C scdir.3 c8d 1 = input, 0 = output. smart card c8 direction. scdir.2 c4d 1 = input, 0 = output. smart card c4 direction. scdir.1 C scdir.0 C downloaded from: http:///
73s1210f data sheet ds_1210f_001 92 rev. 1.4 protocol mode register (sprtcol): 0xfe0d ? 0x03 this register determines the protocol to be use when communicating with the selected sm art card. this register should be updated as required when switching between smart card interfaces. table 85 : the sprtcol register msb lsb scisyn mod9/8b scesyn 0 tmode crcen crcms rcvatr bit symbol function sprtcol.7 scisyn smart card internal synchronous mode - configures internal smart c ard interface for synchronous mode. this mode routes the internal interface buffers for rst, io, c4, c8 to the scctl register bits for direct firmware control. clk is generated by the etu counter. sprtcol.6 mod9/8b synchronous 8/9 bit mode select - for sync mode, in protocols with 9 - bit words, set this bit. the first eight bits read go into the rx fifo and the ninth bit read will be stored in the io (or sio) data bit of the srxctl register. sprtcol.5 scesyn smart card external synchronous mode - configures external smart card interface for synchronous mode. this mode routes the external smart card interface buffers for sio to scectl register bits for direct firmware cont rol. sclk is generated by the etu counter. sprtcol.4 0 reserved bit, must always be set to 0. sprtcol.3 tmode protocol mode select - 0: t=0, 1: t=1. determines which smart card protocol is to be used during message processing. sprtcol.2 crcen crc enab le C 1 = enabled, 0 = disabled. enables the checking/generation of crc/lrc while in t=1 mode. has no effect in t=0 mode. if enabled and a message is being transmitted to the smart card, the crc/lrc will be inserted into the message stream after the last tx byte is transmitted to the smart card. if enabled, crc/lrc will be checked on incoming messages and the value made available to the firmware via the crc ls/ms registers. sprtcol.1 crcms crc mode select C 1 = crc, 0 = lrc. determines type of checking algorithm to be used. sprtcol.0 rcvatr receive atr C 1 = enable atr timeout, 0 = disable atr timeout. set by firmware after the smart card has been turned on and the hardware is expecting atr. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 93 sc clock configuration register (scclk): 0xfe0f ? 0x0c thi s register controls the internal smart card (clk) clock generation. table 86 : the scclk register msb lsb C C iclkfs.5 iclkfs.4 iclkfs.3 iclkfs.2 iclkfs.1 iclkfs.0 bit symbol function scclk .7 C scclk .6 C scclk .5 iclkfs. 5 internal smart card clk frequency select - division factor to determine internal smart card clk frequency. mclk clock is divided by (register value + 1) to clock the etu divider, and then by 2 to generate clk. default ratio is 13. the programmed value in this register is applied to the divider after this value is written, in such a manner as to produce a glitch - free output, regardless of the selection of active interface. a register value = 0 will default to the same effect as register value = 1. s cclk .4 iclkfs.4 scclk.3 iclkfs.3 scclk .2 iclkfs.2 scclk .1 iclkfs.1 scclk .0 iclkfs.0 external sc clock configuration register (sceclk): 0xfe10 ? 0x0c this register controls the external smart card (sclk) clock generation. table 87 : the sceclk register msb lsb C C eclkfs.5 eclkfs.4 eclkfs.3 eclkfs.2 eclkfs.1 eclkfs.0 bit symbol function sceclk.7 C sceclk.6 C sceclk.5 eclkfs.5 external smart card clk frequency select - division factor to determine external smart card clk frequency. mclk clock is divided by (register value + 1) to clock the etu divider, and then by 2 to generate sclk. default ratio is 13. the programmed value in this register is applied to the divider after this value is written, in such a manner as to produce a glitch - free output, regardless of the selection of active interface. a register value = 0 will default to the same effect as register value = 1. sceclk.4 eclkfs.4 sceclk.3 eclkfs.3 sceclk.2 eclkfs.2 sceclk.1 eclkfs.1 sceclk.0 eclkfs.0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 94 rev. 1.4 parity control register (sparctl): 0xfe11 ? 0x00 this register provides the ability to configure the parity circuitry on the sm art card interface. the settings apply to both integrated smart card interfaces. table 88 : the sparctl register msb lsb C dispar brkgen brkdet retran discrx inspe forcpe bit symbol function sparctl.7 C sparctl.6 dispar disable parity check C 1 = disabled, 0 = enabled. if enabled, the uart will check for even parity (the number of 1s including the parity bit is even) on every character. this also applies to the ts during atr. sparctl.5 brkgen break generation disable C 1 = disabled, 0 = enabled. if enabled, and t=0 protocol, the uart will generate a break to the smart card if a pa rity error is detected on a receive character. no break will be generated if parity checking is disabled. this also applies to ts during atr. sparctl.4 brkdet break detection disable C 1 = disabled, 0 = enabled. if enabled, and t=0 protocol, the uart will detect the generation of a break by the smart card. sparctl.3 retran retransmit byte C 1 = enabled, 0 = disabled. if enabled and a break is detected from the smart card (break detection must be enabled), the last character will be transmitted again. this bit applies to t=0 protocol. sparctl.2 discrx discard received byte C 1 = enabled, 0 = disabled. if enabled and a parity error is detected (parity checking must be enabled), the last character received will be discarded. this bit applies to t=0 pr otocol. sparctl.1 inspe insert parity error C 1 = enabled, 0 = disabled. used for test purposes. if enabled, the uart will insert a parity error in every character transmitted by generating odd parity instead of even parity for the character. sparctl.0 forcpe force parity error C 1 = enabled, 0 = disabled. used for test purposes. if enabled, the uart will generate a parity error on a character received from the smart card. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 95 byte control register (sbytectl): 0xfe12 ? 0x2c this register controls the processing of characters and the detection of the ts byte. when receiving, a break is asserted at 10.5 etu after the beginning of the start bit. break from the card is sampled at 11 etu. table 89 : the sbytectl register msb lsb C detts dirts brkdur.1 brkdur.0 C C C bit symbol function sbytectl.7 C sbytectl.6 detts detect ts byte C 1 = next byte is ts, 0 = next byte is not ts. when set, the hardware will treat the next character received as the ts and determine if direct or indirect convention is being used. direct convention is the default used if firmware does not set this bit prior to transmission of ts by the s mart card to the firmware. the hardware will check parity and generate a break as defined by the dispar and brkgen bits in the parity control register. this bit is cleared by hardware after ts is received. ts is decoded prior to the fifo and is stored in the receive fifo. sbytectl.5 dirts direct mode ts select C 1 = direct mode, 0 = indirect mode. set/cleared by hardware when ts is processed indicating either direct/indirect mode of operation. when switching between smart cards, the firmware should write the bit appropriately since this register is not unique to an individual smart card (firmware should keep track of this bit). sbytectl.4 brkdur.1 break duration select C 00 = 1 etu, 01 = 1.5 etu, 10 = 2 etu, 11 = reserved. determines the length of a break signal which is generated when detecting a parity error on a character reception in t=0 mode. sbytectl.3 brkdur.0 sbytectl.2 C sbytectl.1 C sbytectl.0 C downloaded from: http:///
73s1210f data sheet ds_1210f_001 96 rev. 1.4 fd control register (fdreg): 0xfe13 ? 0x11 this register uses the transmission factors f and d to set the etu (baud) rat e. the values in this register are mapped to the iso 7816 conversion factors as described below. the clk signal for each interface is created by dividing a high - frequency, intermediate signal (msclk) by 2. the etu baud rate is created by dividing msclk by 2 times the fi/di ratio specified by the codes below. f or example, if fi = 0001 and di = 0001, the ratio of fi/di is 372/1. thus the etu divider is configured t o divide by 2 * 372 = 744. the maximum supported f/d ratio is 4096. table 90 : the fdreg register msb lsb fval.3 fval.2 fval.1 fval.0 dv al.3 dval.2 dval.1 dval.0 table 91 : the fdreg bit functions bit symbol function fdreg .7 fval.3 refer to the table 93 above. this value is converted per the table to set the divide ratio used to generate the baud rate (etu). default, also used for atr, is 0001 (fi = 372). this value is used by the selected interface. fdreg .6 fval.2 fdreg .5 fval.1 fdreg .4 fval.0 fdreg.3 dval.3 refer to table 93 above. this value is used to set the divide ratio used to generate the smart card clk. default, also used for atr, is 0001 (di = 1). fdreg .2 dval.2 fdreg .1 dval.1 fdreg .0 dval.0 table 92 : divider ratios provided by the etu counter fi (code) 0000 0001 0010 0011 0100 0101 0110 0111 fi (ratio) 372 372 558 744 1116 1488 1860 1860 fclk max 4 5 6 8 12 16 20 20 fi(code) 1000 1001 1010 1011 1100 1101 1110 1111 fi(ratio) 512 512 768 1024 1536 2048 2048 2048 fclk max 5 5 7.5 10 15 20 20 20 di(code) 0000 0001 0010 0011 0100 0101 0110 0111 di(ratio) 1 1 2 4 8 16 32 32 di(code) 1000 1001 1010 1011 1100 1101 1110 1111 di(ratio) 12 20 16 16 16 16 16 16 note: values marked with are not included in the iso definition and arbitrary values have been assigned. the values given below are used by the etu divider to create the etu clock. the ent ries that are not shaded will result in precise clk/etu per iso requirements. shaded areas are not pr ecise but are within 1% of the target value. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 97 table 93 : divider values for the etu clock fi code 0000 0001 0010 0011 0100 0101 di code f d 372 372 558 744 1116 1488 0001 1 744 744 1116 1488 2232 2976 0010 2 372 372 558 744 1116 1488 0011 4 186 186 279 372 558 744 0100 8 93 93 138 186 279 372 1000 12 62 62 93 124 186 248 0101 16 47 47 70 93 140 186 1001 20 37 37 56 74 112 149 0110 32 23 23 35 47 70 93 fi code 0110 1001 1010 1011 1100 1101 di code f d 186 0 512 768 1024 1536 2048 0001 1 3720 1024 1536 2048 3072 4096 0010 2 1860 512 768 1024 1536 2048 0011 4 930 256 384 512 768 1024 0100 8 465 128 192 256 384 512 1000 12 310 85 128 171 256 341 0101 16 233 64 96 128 192 256 1001 20 186 51 77 102 154 20 5 0110 32 116 32 48 64 96 128 downloaded from: http:///
73s1210f data sheet ds_1210f_001 98 rev. 1.4 crc ms value registers (crcmsb): 0xfe14 ? 0xff, (crclsb): 0xfe15 ? 0xff table 94 : the crcmsb register msb lsb crc.15 crc.14 crc.13 crc.12 crc.11 crc.10 crc.9 crc.8 msb lsb crc.7 crc.6 crc.5 crc.4 crc.3 crc.2 crc.1 crc.0 the 16 - bit crc value forms the tx crc word in tx mode (write value) and the rx c rc in rx mode (read value). the initial value of crc to be used when generating a crc to be transmit ted at the end of a message (after the last tx byte is sent) when enabled in t=1 mode. should be reloaded at the beginning of every message to be transmitted. when using crc, both crc registers shoul d be initialized to ff. when using lrc, the crclsb value register should be loaded to 00. when receiving a message, the firmware should load this with the initial value and then read this regist er to get the final value at the end of the message. these registers need to be reloaded for each new message to be received. when in lrc mode, bits (7:0) are used and bits (15:8) are undefined. during lrc /crc checking and generation, this register is updated with the current value and can be read to aid i n debugging. this information will be transmitted to the smart card using the timing specified by the guard time register. when checking crc/lrc on an incoming message (crc/lrc is check ed against the data and crc/lrc), the firmware reads the final value after the message has been received and determines if an error occurred (= 0x1d0f (crc) no error, else error; = 0 (lrc) no error, else error). when a message is received, the crc/lrc is stored in the fifo. the polynomial used to generate and check crc is x 16 + x 12 + x 5 +1. when in indirect convention, the crc is generated prior to the conversion int o indirect convention. when in indirect convention, the crc is checked after the conv ersion out of indirect convention. for a given message, the crc generated (and readable from this regist er) will be the same whether indirect or direct convention is used to transmit the data to the sm art card. the crclsb / crcmsb registers will be updated with crc/lrc whenever bits are being received or transmitted from/to the smart card (even if crcen is not set and in mode t1) . they are available to the firmware to use if desired. downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 99 block guard time register (bgt): 0xfe16 ? 0x10 this register contains the extra guard time value (egt) most - significant bit. the extra guard time indicates the minimum time between the leading edges of the start bit of consecutive char acters. the delay is depends on the t=0/t=1 mode. used in transmit mode. this register also c ontains the block guard time (bgt) value. block guard time is the minimum time between the l eading edge of the start bit of the last character received and the leading edge of the start bit of the first character transmitted. this should not be set less than the character length. the transmission of the firs t character will be held off until bgt has elapsed regardless of the tx data and tx/rx control bit timing. table 95 : the bgt register msb lsb egt.8 C C bgt.4 bgt.3 bgt.1 bgt.2 bgt.0 bit symbol function bgt.7 egt.8 most - significant bit for 9 - bit egt timer. see the egt register. bgt.6 C bgt.5 C bgt.4 bgt.4 time in etus between the start bit of the last received character to start bit of the first character transmitted to the smart card. default value is 22. bgt.3 bgt.3 bgt.2 bgt.2 bgt.1 bgt.1 bgt.0 bgt.0 extra guard time register (egt): 0xf e17 ? 0x0c this register contains the extra guard time value (egt) least - significant byte. the extra guard time indicates the minimum time between the leading edges of the start bit of consecutive char acters. the delay depends on the t=0/t=1 mode. used in transmit mode. table 96 : the egt register msb lsb egt.7 egt.6 egt.5 egt.4 egt.3 egt.1 egt.2 egt.0 bit function egt.7 time in etus between start bits of consecutive characters. in t=0 mode, the minimum is 1. in t=0, the leading edge of the next start bit may be delayed if there is a break detected from the smart card. default value is 12. in t=0 mode, regardless of the value loaded, the minimum value is 12, and for t=1 mode, the minimum value is 11. egt.6 egt.5 e gt .4 egt.3 egt.2 egt.1 egt.0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 100 rev. 1.4 block wait time registers (bwtb0): 0xfe1b ? 0x00, (bwtb1): 0xfe1a ? 0x00, (bwtb2): 0xfe19 ? 0x00, (bwtb3): 0xfe18 ? 0x00 these registers are used to set the block waiting time(27:0) (bwt). all of these parameters define the maximum time the 73s1210f will have to wait for a character from the smart car d. these registers serve a dual purpose. when t=1, these registers are used to set up the block wait time. t he block wait time defines the time in etus between the beginning of the last character sent to smart car d and the start bit of the first character received from smart card. it can be used to detect an unr esponsive card and should be loaded by firmware prior to writing the last tx byte. when t=0, these regist ers are used to set up the work wait time. the work wait time is defined as the time between the leading edge of two consecutive characters being sent to or from the card. if a timeout occurs, an interrupt is generated to the firmware. the firmware can then take appropriate action. a wait time extension (wtx) is supported with the 28 - bit bwt. table 97 : the bwtb0 register msb lsb bwt.7 bwt.6 bwt.5 bwt.4 bwt.3 bwt.1 bwt.2 bwt.0 table 98 : the bwtb1 re gister msb lsb bwt.15 bwt.14 bwt.13 bwt.12 bwt.11 bwt.10 bwt.9 bwt.8 table 99 : the bwtb2 register msb lsb bwt.23 bwt.22 bwt.21 bwt.20 bwt.19 bwt.18 bwt.17 bwt.16 table 100 : the bwtb3 register m sb lsb C C C C bwt.27 bwt.26 bwt.25 bwt.24 character wait time registers (cwtb0): 0xfe1d ? 0x00, (cwtb1): 0xfe1c ? 0x00 these registers are used to hold the character wait time(15:0) (cwt) or initial waiting time(15:0) (iwt) depending on the situation. both the iwt and the cwt measure the time in etus between the leading edge of the start of the current character received from the smart card and the leading edge of the start of the next character received from the smart card. the only difference is the mode i n which the card is operating. when t=1 these registers are used to configure the cwt and these registers conf igure the iwt when the atr is being received. these registers should be loaded prior to receiving charac ters from the smart card. firmware must manage which time is stored in the register. i f a timeout occurs, an interrupt is generated to the firmware. the firmware can then take appropriate action. table 101 : the cwtb0 register msb lsb cwt.7 cwt.6 cwt. 5 cwt.4 cwt.3 cwt.1 cwt.2 cwt.0 table 102 : the cwtb1 register msb lsb cwt.15 cwt.14 cwt.13 cwt.12 cwt.11 cwt.10 cwt.9 cwt.8 downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 101 atr timeout registers (atrlsb): 0xfe20 ? 0x00, (atrmsb): 0xfe1f ? 0x00 these registers form the atr timeout (atrto [15:0]) parameter. time in e tu between the leading edge of the first character and leading edge of the last character of the atr response. t imer is enabled when the rcvatr is set and starts when leading edge of the first start bit is received and disabled when the rcvatr is cleared. an atr timeout is generated if this time is exc eeded. table 103 : the atrlsb register msb lsb atrto.7 atrto.6 atrto.5 atrto.4 atrto.3 atrto.1 atrto.2 atrto.0 table 104 : the atrmsb register msb lsb atrto.15 atrto.14 atrto.13 atrto.12 atrto.11 atrto.10 atrto.9 atrto.8 ts timeout register (ststo): 0xfe21 ? 0x00 the ts timeout is the time in etu between the de - assertion of smart card reset and the leading edge of the ts character in the atr (when detts is set). the timer is start ed when smart card reset is de - asserted. an atr timeout is generated if this time is exceeded (mute card). table 105 : the ststo register msb l sb tst0.7 tst0.6 tst0.5 tst0.4 tst0.3 tst0.1 tst0.2 tst0.0 reset time register (rlength): 0xfe22 ? 0x70 time in etus that the hardware delays the de - assertion of rst. if set to 0 and rstcrd = 0, the hardware adds no extra delay and the hardware will release rst after vccok is asserted during power - up. if set to 1, it will delay the release of rst by the time in this register. when the fi rmware sets the rstcrd bit, the hardware will assert reset (rst = 0 on pin). when firmware clears the bit, the hardware will release rst after the delay specified in rlen. if firmware sets the rstcrd bit prior to instructing the power to be applied to the smart card, the hardware will not release rst after power - up until rlen after the firmware clears the rstcrd bit. this provides a means to power up the smart card and hold it in reset until the firm ware wants to release the rst to the selected smart card. works with the selected smart card interface. table 106 : the rlength register msb lsb rlen .7 rlen .6 rlen .5 rlen .4 rlen .3 rlen .1 rlen .2 rlen .0 downloaded from: http:///
73s1210f data sheet ds_1210f_001 102 rev. 1.4 shaded locations indicate functions that are not provided in the synchronous mode. table 107 : smart card sfr table name address b7 b6 b5 b4 b3 b2 b1 b0 scsel fe00 selsc(1:0) bypass scint fe01 waitto/ rlien crdevt vcctmr rxdavl txevnt txsent txerr rxerr scie fe02 wtoi/ rlien cdevnt vtmren rxdaen txeven txsnten txerr rxerr vccctl fe03 vccsel.1 vccsel.0 vddflt rdyst vccok scpwrdn vcctmr fe04 offtmr(3:0) vcctmr(3:0) crdctl fe05 deboun cdeten detpol puenb pden cardin stxctl fe06 i2cmode txfull txemty txundr lasttx tx/rxb breakd stxdata fe07 txdata(7:0) srxctl fe08 bit9dat lastrx crcerr rxfull rxemty rxovrr paritye srxdata fe09 rxdata(7: 0) scctl fe0a rstcrd io iod c8 c4 clklvl clkoff scectl fe0b sio siod sclklvl sclkoff scdir fe0c c8d c4d sprtcol fe0d scisyn mod9/8 b scesyn 0 tmode crcen crcms rcvatr scclk fe0f iclkfs(5:0) sceclk fe10 eclkfs(5:0) sparctl fe11 dispar brkgen brkdet rtran discrx inspe forcpe sbytectl fe12 detts dirts brkdur (1:0) fdreg fe13 fval(3:0) dval (3:0) crcmsb fe14 crc(15:8) crclsb fe15 crc(7:0) bgt fe16 egt8 b gt(4:0) egt fe17 egt(7:0) bwtb3 fe18 bwt(27:24) bwtb2 fe19 bwt(23:16) bwtb1 fe1a bwt(15:8) bwtb0 fe1b bwt(7:0) cwtb1 fe1c cwt(15:8) cwtb0 fe1d cwt(7:0) atrmsb fe1f atrto(15:8) atrlsb fe20 atrto(7:0) ststo fe21 tsto(7:0) rlength fe22 rlen(7:0) downloaded from: http:///
ds_1210f_001 73s1210f data sheet rev. 1.4 103 1.7.16 vdd fault detect function the 73s1210f contains a circuit to detect a low - voltage condition on the supply voltage v dd . if enabled, it will deactivate the active internal smart card interface when v dd falls below the v dd fault threshold. the register configures the v dd fault threshold for the nominal default of 2.3v* or a user selectable threshold. the users code may load a different value using the fovrvddf bit = 1 after the pow er - up cycle has completed. vddfaul t control register (vddfctl): 0xffd4 ? 0x00 table 108 : the vddfctl register msb lsb C fovrvddf vddflten C stxdat.3 vddfth .2 vddfth .1 vddfth .0 bit symbol function vddfctl .7 C vddfctl .6 fovrvddf setting this bit high will allow the vddflt(2:0) bits set in this register to control the vddfault threshold. when this bit is set low, the vddfault threshold wi ll be set to the factory default setting of 2.3v*. vddfctl .5 vddflten set = 1 will disable vdd fault operation. vddfct l .4 C vddfctl.3 C vddfctl .2 vddfth.2 vdd fault threshold. bit value(2:0) vddfault voltage 000 2.3 (nominal default) 001 2.4 010 2.5 011 2.6 100 2.7 101 2.8 110 2.9 111 3.0 vddfctl .1 vddfth.1 vddfctl .0 vddfth.0 * note: the v dd fault factory default can be set to any threshold as defined by bits vddfth(2:0). the 73s1210f has the capability to burn fuses at the factory to set the factory default to any of these voltages. contact teridian for further details. downloaded from: http:///
73s1210f data sheet ds_1210f_001 104 rev. 1.4 2 typical application schem atic smartcardslot #1 c5 0.1uf y1 12.000mhz e vdd x 0 d a 9 on/ce 2 4 f f1 clr optional lcd display system16 character by 2 lines 8 / down 30-switchkeypad lcdbrightness adjust on_off y 5 f3 1 c 6 . smartcardslot #2 z w c19 0.1uf r1 1m + c15 1uf c7 4.7uf gnd 1 gnd 2 vpc 3 nc 4 nc 5 nc 6 pres 7 i/o 8 nc 9 a u x2 10 a u x1 11 gnd 12 clk 13 rst 14 vcc 15 nc 16 vddf_adj 17 scl 18 sda 19 vdd 20 gnd 21 int 22 xtalin 23 xtalout 24 nc 25 i/ouc 26 aux1uc 27 aux2uc 28 sad0 29 sad1 30 sad2 31 nc 32 u3 73s8010r r70 l1 10uh vdd c16 27p c18 1.0uf c17 27p + c4 10uf c6 10uf vdd 68 reset 1 sec 2 isbr 3 scl 5 sda 6 n/c 7 n/c 8 gnd 9 x12in 10 x12out 11 col0 12 col1 13 col2 14 anain 15 col3 16 rxd 17 txd 18 col4 19 usr7 20 row0 21 row1 22 usr6 23 row2 24 gnd 25 n/c 26 n/c 27 vdd 28 usr5 29 usr4 30 usr3 31 usr2 32 row3 33 usr1 34 usr0 35 row4 36 row5 37 erst 38 tclk 39 vdd 40 tbus3 41 gnd 42 rxtx 43 tbus2 44 sclk 45 tbus1 46 sio 47 int3 48 int2 49 tbus0 50 test 51 off_req 52 pres 53 vp 54 clk 55 gnd 56 rst 57 vcc 58 c8/aux2 59 c4/aux1 60 i/o 61 vbus 62 on_off 63 vbat 64 vpc 65 lin 66 gnd 67 slug 69 led0 4 u1 73s1210f d1 led c11 0.1uf c10 0.47uf c2 22pf c12 0.1uf c13 0.1uf c14 0.1uf vdd host serial rx host serial tx vo 3 vdd 2 db0 7 nc 15 gnd 1 rs 4 r/w* 5 e 6 db7 14 db6 13 db5 12 db4 11 db3 10 db2 9 db1 8 u2 1 2 s11 sw vdd 1 3 s1 sw_mom usr2 usr4 usr1 usr5 usr0 usr3 usr6 input power supply (2.7 - 6.5v) vdd c9 27p 1 3 s2 sw_mom 1 3 s3 sw_mom 1 3 s4 sw_mom 1 3 s5 sw_mom c8 27p r6 20k r4 10k 1 3 s6 sw_mom 1 3 s12 sw_mom 1 3 s17 sw_mom r2 3k 1 3 s22 sw_mom 1 3 s27 sw_mom r8 100 1 3 s7 sw_mom 1 3 s13 sw_mom 1 3 s18 sw_mom 1 3 s23 sw_mom 1 3 s28 sw_mom 1 3 s8 sw_mom d2 5.0v zener 1 3 s14 sw_mom 1 3 s19 sw_mom 1 3 s24 sw_mom c3 0.1uf 1 3 s29 sw_mom 1 3 s9 sw_mom 1 3 s15 sw_mom 1 3 s20 sw_mom 1 3 s25 sw_mom 1 3 s30 sw_mom 1 3 s16 sw_mom 1 3 s10 sw_mom 1 3 s21 sw_mom 1 3 s26 sw_mom 1 3 s31 sw_mom r3 3k vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j1 smart card connector c1 22pf enter up 7 usr1 usr2 usr6 usr5 usr4 usr3 r9 20k r5 0 vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j2 smart card connector vdd usr0 f2 3 b 1 3 2 cw rv1 10k figure 25 : 73s1210f typical application schematic downloaded from: http:///
ds_7310f_001 73s1210f data sheet rev. 1.4 105 3 electrical specification 3.1 absolute maximum ratings operation outside these rating limits may cause permanent damage to the device. the smart card interface pins are protected against short circuits to v cc , ground, and each other. p ar am et er r at i n g dc supply voltage, v dd - 0.5 to 4.0 vdc supply voltage v pc - 0.5 to 6.6 vdc supply voltage v bus - 0.5 to 6.6 vdc supply voltage v bat - 0.5 to 6.6 vdc storage temperature - 60 to 150 c pin voltage (except card interface) - 0.3 to (v dd +0.5) vdc pin voltage (card interface) - 0.3 to (v cc +0.5) vdc esd tolerance (except card interface) +/ - 2kv esd tolerance (card interface) +/ - 7kv pin current 200 ma note: esd testing on smart card pins is hbm condition, 3 pulses, each polarity referenced to ground. note: smart card pins are protected against shorts between any combinations of smart card pins. 3.2 recommended operating conditions unless otherwise noted all specifications are valid over these temperatures and supply v oltage ranges: parameter rating supply voltage v pc 2.7 to 6.5 vdc supply voltage v bus 4.4 to 5.5 vdc supply voltage v bat 4.0 to 6.5 vdc ambient operating temperature (ta) - 40 c to +85 c downloaded from: http:///
73s1210f data sheet ds_1210f_001 106 rev. 1.4 3.3 digital io characteristics these requirements pertain to digital i/o pin types with consideration of the specifi c pin function and configuration. the led(1:0) pins have p ull - ups that may be enabled. the row pins have 100k ? pull - ups. symbol parameter conditions min. typ. max. unit voh output level, high ioh = - 2ma 0.8 * v dd v dd v off_req pin - i oh = - 1ma v dd - 0.45 v vol output level, low iol = 2ma 0 0.3 v off _req pin - iol = 2ma 0.45 v vih input voltage, high 2.7v < vdd <3.6v 1.8 v dd +0.3 v vil input voltage, low 2.7v < vdd <3.6v - 0.3 0.6 v reset, on_off,pres pins - 0.3 0.8 v ileak leakage current 0 < vin < vdd all output modes disabled, pull - up/down s disabled -5 5 a ipu pull - up current if provided and enabled, vout < 0.1v -5 a ipd pull - down current if provided and enabled, vout > vdd C 0.1v 5 a symbol parameter conditions min. typ. max. unit iled led drive current vout = 1.3v, 2.7v < vd d < 3.6v 2 4 10 ma iolkrow keypad row output low current 0.0v < voh < 0.1v when pull - up r is enabled 40 100 a iolkcol keypad column output high current 0.0v < voh < 0.1v when col. is pulled low 1.5 3 ma downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 107 3.4 oscillator interface requirements symbol pa rameter condition min typ. max unit high - frequency oscillator (xin) parameters. xin is used as input for externa l clock for test purposes only. a resistor connecting x12in to x12out is required, valu e = 1m ?. vilx12in input low voltage C x12in - 0.3 1.5 0.3*vdd v vihx12in input high voltage C x12in 0.7*vdd 1.6 vdd+.0.3 v iilxtal input current - x12in gnd < vin < vdd - 10 10 a fxtal crystal resonant frequency fundamental mode 6 12 mhz 3.5 dc characteristics: analog input symbol parameter condition min typ. max unit v thtol voltage threshold tolerance selected threshold value - 3% +3% v downloaded from: http:///
73s1210f data sheet ds_1210f_001 108 rev. 1.4 3.6 smart card interface requirements symbol parameter condition min typ. max unit card power supply (v cc ) regul ator general conditions, - 40 c < t < 85 c, 4.75v < v pc < 6.0v, 2.7v < v dd < 3.6v v cc card supply voltage including ripple and noise inactive mode - 0.1 0.1 v inactive mode, i cc = 1ma - 0.1 0.4 v active mode; i cc <65ma; 5v 4.65 5.25 v active mo de; i cc < 65ma; 3v 2.85 3.15 v active mode; i cc < 40ma; 1.8v 1.68 1.92 v active mode; single pulse of 100ma for 2 s; 5v, fixed load = 25ma 4.6 5.25 v active mode; single pulse of 100ma for 2 s; 3v, fixed load = 25ma 2.76 3.15 v active mode; current pulses of 40nas with peak |i cc | <200ma, t <400ns; 5v 4.6 5.25 v active mode; current pulses of 40nas with peak |i cc | <200ma,t <400ns; 3v 2.7 3.15 v active mode; current pulses of 20nas with peak |i cc | <100ma,t <400ns; 1.8v 1.62 1.92 v v ccrip v cc ripple f ripple = 20khz C 200mhz 350 mv i ccmax card supply output current static load current, v cc >1.65 40 ma static load current, v cc >4.6v or 2.7v as selected 65 ma i ccf i cc fault current class a, b (5v and 3v) 100 180 ma class c (1.8v) 60 130 isc maximum current prior to shut - down load current limit prior to vcc shut - down 80 150 ma. load current limit prior to vcc shut - down for vcc = 1.8v 60 130 ma v sr vcc slew rate, rise rise rate on activate c = 0.47 f 0.12 .30 0.50 v/ s v sf vcc slew rate, fall fall rate on deactivate, c = 0.47 f 0.15 .30 1.20 v/ s v rdy vcc ready voltage (vccok = 1) 5v operation, vcc rising 4.6 v 3v operation, vcc rising 2.75 v 1.8v operation, vcc rising 1.65 v downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 10 9 symbol parameter condi tion min typ. max unit interface requirements C data signals: i/o, aux1 and aux2 v oh output level, high i oh = 0 0.9 * v cc v cc +0.1 v i oh = - 40 a 0.75 v cc v cc +0.1 v v ol output level, low i ol = 1ma 0.15 *v cc v v ih input level, high 0.6 * v cc v cc +0.30 v v il input level, low - 0.15 0.2 * v cc v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i leak input leakage v ih = v cc 10 a i il input current, low v il = 0 0.65 ma i il input current, low v il = 0 0.7 ma i shortl short circuit output current for output low, shorted to v cc through 33 ? 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? 15 ma t r , t f output rise time, fall times for i/o, aux1, aux2, c l = 80pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl = 50pf, 10% to 90%. 100 ns t ir , t if in put rise, fall times 1 s r pu internal pull - up resistor output stable for >200ns 8 11 14 k ? fd max maximum data rate 1 mhz reset and clock for card interface, rst, clk v oh output level, high i oh = - 200 a 0.9 * v cc v cc v v ol output level, low i ol = 200 a 0 0.15 * v cc v v inact output voltage when outside of session i ol = 0 0.1 v i ol = 1ma 0.3 v i rst_lim output current limit, rst 30 i clk_lim output current limit, clk 70 ma t r , t f output rise time, fall time c l = 35pf for clk, 10% to 90% 8 ns c l = 200pf for rst, 10% to 90% 100 ns duty cycle for clk c l = 35pf, f clk 20mhz, clkin duty cycle is 48% to 52%. 45 55 % downloaded from: http:///
73s1210f data sheet ds_1210f_001 110 rev. 1.4 3.7 dc characteristics symbol parameter condition min typ. max unit i pc supply current @ v pc = 2.7v (v bus a nd v bat unconnected) cpu clock @ 24mhz 44 55 66 ma cpu clock @ 12mhz 31 38 46 ma cpu clock @ 6mhz 23 29 35 ma cpu clock @ 3.69mhz 20 25 30 ma supply current @ v pc = 3.3v (v bus and v bat unconnected) cpu clock @ 24mhz 34 43 51 ma cpu clock @ 12 mhz 24 30 36 ma cpu clock @ 6mhz 18 22 27 ma cpu clock @ 3.69mhz 16 19 23 ma supply current @ v pc = 5.0v (v bus and v bat unconnected) cpu clock @ 24mhz 20 25 30 ma cpu clock @ 12mhz 14 18 21 ma cpu clock @ 6mhz 11 13 16 ma cpu clock @ 3.69m hz 9 12 14 ma i vbus supply current @ v vbus = 4.4v cpu clock @ 24mhz 16 20 24 ma cpu clock @ 12mhz 11 14 17 ma cpu clock @ 6mhz 8 10 13 ma cpu clock @ 3.69mhz 7 9 11 ma supply current @ v vbus = 5.0v cpu clock @ 24mhz 16 19 23 ma cpu clock @ 12mhz 11 14 17 ma cpu clock @ 6mhz 8 10 13 ma cpu clock @ 3.69mhz 7 9 11 ma supply current @ v vbus = 5.5v cpu clock @ 24mhz 16 20 23 ma cpu clock @ 12mhz 11 14 17 ma cpu clock @ 6mhz 8 11 13 ma cpu clock @ 3.69mhz 7 9 11 ma i vbat supply current @ v vbat = 4.0v (v bus = 0v) cpu clock @ 24mhz 28 34 41 ma cpu clock @ 12mhz 19 24 28 ma cpu clock @ 6mhz 14 18 21 ma cpu clock @ 3.69mhz 12 15 19 ma supply current @ v vbat = 5.0v (v bus = 0v) cpu clock @ 24mhz 20 26 31 ma cpu clock @ 12 mhz 14 18 21 ma cpu clock @ 6mhz 11 13 16 ma cpu clock @ 3.69mhz 9 12 14 ma supply current @ v vbat = 6.5v (v bus = 0v) cpu clock @ 24mhz 16 20 24 ma cpu clock @ 12mhz 11 14 17 ma cpu clock @ 6mhz 8 10 13 ma cpu clock @ 3.69mhz 7 9 11 ma v dd * v dd supply voltage 2.7v < vpc < 6.5v, i vdd < 40ma. 3.0 3.3 3.6 v downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 111 i dd_in supply current C pins 28 + 40 (internal consumption C digital core) cpu clock @ 24mhz 29 33.5 ma cpu clock @ 12mhz 21 24 ma cpu clock @ 6mhz 15.5 18 ma cpu c lock @ 3.69mhz 13.5 15.5 ma power down (- 40 to 85 c) 8 50 a power down (25 c) 6 15 a i dd_out supply current C pin 68 (available to external circuitry) circuit on 20 ma i vbus supply current from v bus v cc off, i ddinternal < 20 a 0.2 0.4 ma i vbat i vpc supply current from v bat or v pc circuit off 0.01 1 a vbus on v bus detection threshold 3.5 v vbus idis v bus discharge current 50 a e x t er n al c ap ac i t o r v al u es c vpc external filter capacitor for v pc 8.0 10.0 12.0 f c vp external filter capacitor for v p 2.0 4.7 10.0 f c vdd * external filter capacitors for v dd 0.2 1.0 f c vcc external filter capacitor for v cc c vcc should be ceramic with low esr (<100m ? ). 0.2 0.47 1.0 f *note: recommend on 0.1 f for each v dd pin. 3.8 current fault detection circuits symbol parameter condi tion min typ. max unit iv pmax v p over current fault 150 ma i ddmax vdd over - current limit 40 100 ma i ccf card overcurrent fault 80 150 ma i ccf1p8 card overcurrent fault v cc = 1.8v 60 130 ma downloaded from: http:///
73s1210f data sheet ds_1210f_001 112 rev. 1.4 4 equivalent circuits vdd x12lin x12out enable ttl to circuit esd esd fig ure 26 : 12 mhz oscillator circuit vdd x32lin x32out enableb ttl to circuit >1meg esd esd figure 27 : 32khz oscillator circuit downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 113 pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable esd figure 28 : digital i/o circuit pin vdd strong pfet strong nfet data from circuit output disable esd figure 29 : digital output circuit downloaded from: http:///
73s1210f data sheet ds_1210f_001 114 rev. 1.4 pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable very weak pfet esd figure 30 : digital i/o with pull up circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable very weak nfet pull-down enable esd figure 31 : digital i/o with pull d own circuit downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 115 pin ttl to circuit esd figure 32 : digital input circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable esd very weak pfet very weak nfet pull-down enable esd figure 33 : off_req interface circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit output disable pull-up disable 100k ohm esd figure 34 : keypad row circuit downloaded from: http:///
73s1210f data sheet ds_1210f_001 116 rev. 1.4 pin vdd medium pfet strong nfet data from circuit ttl to circuit output disable esd 1200 ohms figure 35 : keypad column circuit pin vdd strong pfet strong nfet data from circuit ttl to circuit pullup disable 0, 2, 4, 10ma current value control esd figure 36 : led circuit downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 117 pin vih>0.7*vdd to circuit logic r= 20k ? this buffer has a special input threshold: esd figure 37 : test and security pin circuit pin to comparator input esd figure 38 : analog input circuit pin vcc strong pfet strong nfet from circuit esd esd figure 39 : smart card output circuit downloaded from: http:///
73s1210f data sheet ds_1210f_001 118 rev. 1.4 125ns delay io pin vcc strong pfet strong nfet rl=11k from circuit cmos to circuit esd esd figure 40 : smart card i/o circuit pin ttl to circuit very weak nfet pull-down enable esd esd vdd figure 41 : pres input circuit pin vdd ttl to circuit pull-up disable esd very weak pfet pull-down enable esd figure 42 : presb input circuit downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 119 pin to circuit logic r= 24k ? esd vpc figure 43 : on_off input circuit downloaded from: http:///
73s1210f data sheet ds_1210f_001 120 rev. 1.4 5 package pin designation 5.1 68 - pin qfn pinout figure 44 : 73s1210f 68 qfn pinout caution: use handling procedures necessary for a static sensitive component teridian 73s1210f col 4 usr1 row 3 usr3 usr4 usr5 vdd n/c n/c gnd row 2 usr6 row 1 row 0 usr7 tbus0 test vp vbus clk gnd rst vcc aux2 aux1 io pres on _ off vbat lin gnd vdd sec scl sda n/c n/c gnd xi2in x12out col0 col1 col2 ana_in col3 rxd txd int3 sio tbus1 sclk tbus2 rxtx gnd tbus3 vdd tclk erst row5 row4 usr0 isbr reset usr2 int2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 off _req vpc led0 1 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 121 5.2 44 - pin qfn pinout teridian 73s1210f usr1 usr2 usr3 usr4 usr5 vdd gnd usr6 usr7 test vpc pres clk gnd rst vcc aux2 aux1 io on _ off lin led0 scl sda gnd xi2in x12out rxd txd sio sclk rxtx vdd erst usr0 vdd int3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 1213 1415 16 17 33 32 31 30 29 28 27 26 25 24 23 tclk 4443 42 41 4039 38 37 36 35 34 reset gnd gnd int2 off_req vp figure 45 : 73s1210f 44 qfn pinout caution: use handling procedures necessary for a static sensitive component. downloaded from: http:///
73s1210f data sheet ds_1210f_001 122 rev. 1.4 6 packaging information 6.1 68 - pin qfn package outline notes: 6.3mm x 6.3mm exposed pad area must remain unconnected (clear of pcb traces or vias). controlling dimensions are in mm. top view seating plane 12 side view 68 12 3 8. 00 7. 75 8. 00 7. 75 0. 00 /0. 05 0.2 0. 85 0. 65 terminal tip for odd terminal / side l c c c 0. 40 scale : none section "c-c" 0. 20 0. 15 /0. 25 0. 00 /0. 05 bottom view 68 pin # 1 id r0. 20 0. 45 8. 00 8. 00 6. 30 6. 15 /6. 45 0. 42 0. 24 /0. 60 0. 42 0. 24 /0. 60 6. 40 6. 40 6. 30 6. 15 /6. 45 1 2 3 figure 46 : 73s1210f 68 qfn mechanical drawing downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 123 6.2 44 - pin qfn package outline notes: 5.1mm x 5.1mm exposed pad area must remain unconnected (clear of pcb traces or vias). controlling dimensions are in mm. top view seating plane 12 side view 44 1 23 7. 00 6. 75 7. 00 6. 75 0. 00 /0. 05 0.2 0. 85 0. 65 terminal tip for odd terminal / side l c c c 0. 50 scale : none section "c-c" 0. 23 0. 18 /0. 30 0. 00 /0. 05 bottom view 44 pin # 1 id r0. 20 0. 45 7. 00 7. 00 5. 10 4. 95 /5. 25 0. 42 0. 24 /0. 60 0. 42 0. 24 /0. 60 5. 00 5. 00 5. 10 4. 95 /5. 25 1 2 3 figure 47 : 73s1210f 44 qfn package drawing downloaded from: http:///
73s1210f data sheet ds_1210f_001 124 rev. 1.4 7 ordering information table 109 lists the order numbers and packaging marks used to identify 73s1210f products. table 109 : order numbers and packaging marks part description order number packaging mark 73s1210f 68 - pin qfn, lead free 73s1210f 68 - pin qfn, lead free with programming 73s1210f - 68im/f 73s1210f - 68im / f/p 73s1210f68im 73s1210f68im 73s1210f 68 - pin qfn, lead free, tape and re el 73s1210f 68 - pin qfn, lead free, tape and reel with programming 73s1210f - 68imr/f 73s1210f - 68imr / f/p 73s1210f68im 73s1210f68im 73s1210f 44 - pin qfn, lead free 73s1210f 44 - pin qfn, lead free with programming 73s1210f - 44im/f 73s1210f - 44im /f /p 73s1210f44im 7 3s1210f44im 73s1210f 44 - pin qfn, lead free, tape and reel 73s1210f 44 - pin qfn, lead free, tape and reel with programming 73s1210f - 44imr/f 73s1210f - 44imr /f/p 73s1210f44im 7 3s1210f44im 8 related documentation the following 73s1210f documents are available from teridian semiconductor corporation: 73s1210f data sheet (this document) 73s1210f development board quick start guide 73s1210f software development kit quick start guide 73s1210f evaluation board users guide 73s12xx f software users guide 73s12xxf synchronous card design application note 9 contact information for more information about teridian semiconductor products or to check the availability of the 73s1210f, contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 -8 800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ds_1210f_001 73s1210f data s heet rev. 1.4 125 revision history revision date description 1.0 5/10/2007 first publicat ion. 1.1 11/6/2007 in table 1 , added equivalent circuit references. in section 1.4 , updated program security description to remove pre - boot and 32 - cycle references. in section 1.7.1 , changed mcount is configured in the mclkctl register must be bound between a value of 1 to 7. the possible crystal or external clock are shown in table 12. to mcount is configured in the mclkctl register must be bound between a value of 1 to 7. the possible crystal or external clock frequencies for getting mclk = 96mhz are shown in table 11 . in the brcon description, changed if bsel = 1, the baud rate is derived using timer 1. to if bsel = 0, the baud rate is derived using timer 1. in section 1.7.14 , removed the following from the emulator port description: the signals of the emulator port have weak pull - ups. adding resistor footprints for signals e_rst, e_tclk and e_rxtx on the pcb is recommended. if necessary, adding 10k ? pull - up resistors on e_tclk and e_rxtx and a 3k ? on e_rst will help the emulator operate normally if a problem arises. in or dering information , removed the leaded part numbers. 1.2 12 / 15/2008 in table 1 , added the pin (44 qfn) column. in table 1 , added more description to the scl, sda, pres , vcc, vpc, sec, test and vdd pins. in section 1.3.2 , changed flsh_erase to erase and flsh_pgadr to pgaddr. added the pgaddr register denotes the page address for page erase. the page size is 512 (200h) bytes a nd there are 128 pages within the flash memory. the pgaddr denotes the upper seven bits of the flash memory address such that bit 7:1 of the pgaddr corresponds to bit 15:9 of the flash memory address. bit 0 of the pgaddr is not used and is ignored. in the description of the pgaddr register , added note: the page address is shifted left by one bit (see detailed description above). in table 5 , changed flshcrl to flshctl. in table 5 , removed the preboot bit description. in table 5 , moved the trimpctl bit description to fusectl and moved the fusectl bit description to trimpctl. in table 6 , changed pgadr to pgaddr. in table 7 , added pgaddr. in table 8 , changed the reset value for rtcctl from 0x81 to 0x00. added the rtctrim0 and acomp registers . deleted the omp, vrctl, ledcal and lockctl registers. in table 7 , removed the mcount 7 row. in table 50 through table 53 , changed the names of registers usrintctl0 through usrintctl3 to usrintctl1 through usrintctl4. in tcon , corrected the descriptions for tcon.2 and tcon.0. in section 1.7.9 , added a note about usr pins defaulting as inputs after reset. changed the register address for atrmsb from fe21 to fe1f. downloaded from: http:///
73s1210f data sheet ds_1210f_001 126 rev. 1.4 in section 1.7.15.5 , deleted the etu clock is held in reset condition until the activation sequence begins (either by vccok=1 or vcctmr timeout) and will go high ? the etu period thereafter. in section 1.7.15.5 , added synchronous card operation is broken down into three primary types. these are commonly referred to as 2 - wire, 3- wire and i2c synchronous cards. each card type requires different control and timing and therefore requires different algorithms to access. teridian has created an application note to provide detailed algorithms for each card type. refer to the application note titled 73s12xxf synchronous card design application note . in table 78 and table 107 , changed the syckst bit to i2cmode. in figure 25 , replaced the schematic with a new schematic. in section 3.4 , changed the fxtal min from 4 to 6. added 44 - pin qfn package . added secti on 8, related documentation . added section 9, contact information . formatted the document per new standard. added section numbering. 1.3 1/22/2009 changed the value for the i dd_in power down (25 c) parameter from 13 a to 15 a. 1.4 5/12/2009 in table 1 , corrected the 44 qfn gnd pin from 37 to 26. added the with programming ordering number s to table 109 . ? 2009 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor c orporation. windows is a registered trademark of microsoft corporation. signum systems is a trademark of signum systems corporation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the companys warranty detailed in the teridian semiconductor corporation standard terms and conditions. the company assumes no responsibility for any errors which may appear i n this document, reserves the right to change devices or specifications detailed herein at any ti me without not ice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales r epresentative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com downloaded from: http:///

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